Saurabh Saxena
Assistant Professor
+91-44 2257 4457 (Work)
Publications - 42Publications - 42
Publications - 42Publications (42)
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ConferencesA 2.25 GHz PLL with 0.05-2 MHz Inloop Phase Modulation and -70 dBc Reference Spur for Telemetry Applications2023 | IEEE Computer Society- ConferencesA 105-525MHz Integer-N Phase-Locked Loop in Indigenous SCL 180nm CMOS2023 | IEEE Computer Society
- ArticlesA 1.12-1.91 mW/GHz 2.46-4.92 GHz Cascaded Clock Multiplier in 65 nm CMOS2022 | Institute of Electrical and Electronics Engineers Inc.
- ConferencesA 5-Gb/s PAM4 Voltage Mode Transmitter with Current Mode Continuous Time Linear Equalizer2022 | Institute of Electrical and Electronics Engineers Inc.
- ArticlesA 2.5-5.0-GHz Clock Multiplier With 3.2-4.5-mUIrmsJitter and 0.98-1.06 mW/GHz in 65-nm CMOS2022 | Institute of Electrical and Electronics Engineers Inc.
- ArticlesIntentional Electromagnetic Interference Reception in 0.5-2.0 GHz2022 | Institute of Electrical and Electronics Engineers Inc.
- ConferencesA Class-C Injection-Locked Tripler with 48 dB Sub-Harmonic Suppression and 15 fs Additive RMS Jitter in 0.13μm BiCMOS Process2022 | Institute of Electrical and Electronics Engineers Inc.
- ConferencesA 2.5-5GHz injection-locked clock multiplier with embedded phase interpolator in 65nm CMOS2020 | Institute of Electrical and Electronics Engineers Inc.
- Book ChapterDigital clock and data recovery circuits2020 | Institution of Engineering and Technology
JournalA reconfigurable 0.1-10 Gb/s voltage-mode transmitter with 0.2-1V output swing2019 | Institute of Electrical and Electronics Engineers Inc.- ArticlesLow-Jitter Multi-Output All-Digital Clock Generator Using DTC-Based Open Loop Fractional Dividers2018 | Institute of Electrical and Electronics Engineers Inc.
- ArticlesArea and Current Efficient Capacitor-Less Low Drop-Out Regulator Using Time-Based Error Amplifier2018 | Institute of Electrical and Electronics Engineers Inc.
- ArticlesA 1-to-2048 fully-integrated cascaded digital frequency synthesizer for low frequency reference clocks using scrambling TDC2017 | Institute of Electrical and Electronics Engineers Inc.
Open Access - ArticlesA 2.8 mW/Gb/s, 14 Gb/s Serial Link Transceiver2017 | Institute of Electrical and Electronics Engineers Inc.
- ConferencesA 3-to-10Gb/s 5.75pJ/b transceiver with flexible clocking in 65nm CMOS2017 | Institute of Electrical and Electronics Engineers Inc.
- ArticlesA 5GHz Digital Fractional-N PLL Using a 1-bit Delta-Sigma Frequency-to-Digital Converter in 65 nm CMOS2017 | Institute of Electrical and Electronics Engineers Inc.Open Access
