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A 105-525MHz Integer-N Phase-Locked Loop in Indigenous SCL 180nm CMOS
S. Nigam, M. Murali, H.S. Gupta,
Published in IEEE Computer Society
Volume: 2023-January
Pages: 348 - 352
We present an integer-N phase-locked loop with a 5X output frequency range. The charge-pump current and voltage-controlled oscillator's current source are digitally reconfigured for an optimum PLL bandwidth with low output jitter across the 5X frequency range. Fabricated in indigenous SCL 180nm CMOS technology, the PLL multiplies the reference frequency 15-75MHz by seven and generates a 105-525MHz output frequency. It achieves an integrated jitter of 4ps and 32.2ps at 525MHz and l05MHz, respectively. The PLL dissipates 5.6mW and 3.6mW at 525MHz and l05MHz output frequencies while operating from 1.8V supply voltage. © 2023 IEEE.
About the journal
JournalProceedings of the IEEE International Conference on VLSI Design
PublisherIEEE Computer Society