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A 2.25 GHz PLL with 0.05-2 MHz Inloop Phase Modulation and -70 dBc Reference Spur for Telemetry Applications
S. Jakkoju, D.J. Bandarupalli, A. Srikanth, S. Thomas,
Published in IEEE Computer Society
Volume: 2023-January
Pages: 87 - 91
In this paper, we demonstrate a wideband inloop phase modulation in an analog phase-locked loop for telemetry applications. PLLs have contradicting bandwidth requirements for low output reference spur and wideband inloop phase or frequency modulation. To overcome this challenge, we employ a two-point modulation at the input and output of the loop filter, thereby extending the modulation bandwidth. Using off-the-shelf PLL components, opamps, and passive components, a 2.25 GHz PLL with inloop phase modulation is analyzed and implemented on a PCB. The prototype is measured with an onboard 40 MHz crystal to have 340 fsrms integrated jitter and -70 dBc reference spur at the output. The prototype achieves a > 2 MHz -3 dB modulation bandwidth with small modulating amplitudes. An output phase modulation with modulation index m≤ 2 and modulation error Δm < 0.1 across 0.05-2.0 MHz frequency range is realized. © 2023 IEEE.
About the journal
JournalProceedings of the IEEE International Conference on VLSI Design
PublisherIEEE Computer Society