IIT Madras is a public technical and research university located in Chennai, Tamil Nadu. Founded in 1959, it is recognised as an Institute of National Importance.

IIT Madras has been ranked as the top engineering institute in India for four years in a row by the National Institutional Ranking Framework of the MHRD

It currently offers undergraduate, postgraduate and research degrees across 16 disciplines in Engineering, Sciences, Humanities and Management. About 596 faculty belonging to science and engineering departments and centres of the Institute are engaged in teaching, research and industrial consultancy.

IIT Madras

The catalytic pyrolysis of different types of polyoleﬁn and multilayer packaging based plastic wastes in the presence of commercial zeolite catalyst was studied in the batch pilot scale reactor. Different types of multi-layer plastics such as biaxial oriented polypropylene (BOPP), metalized biaxial oriented polypropylene layers (MET/BOPP), poly ethylene terepthalate (PET), metalized polyethylene-terepthalate (MET/PET), PET combined polyethylene (PET/PE) and mixed polyolefin plastic wastes obtained from the municipal corporation were pyrolyzed to determine the oil, gas and char distribution. BOPP based plastic waste exhibited higher oil yield and calorific value (65–70%, 45.14 KJ/g) compared to PET based MLPs (17.8 %, 30 KJ/g) and laminated metalized plastics (13 %, 37 KJ/g). Modifying the feed composition by mixing of polyolefins-based waste plastics with PET based MLPs and BOPP/MET BOPP doubled the liquid yield and notably altered the physicochemical characterization of the resulted pyrolysis oil. Char yield in the polyolefins-based waste is observed to be lesser than the MLP based waste plastics. GC–MS analysis revealed the percentage area of hydrocarbons compounds of the pyrolysis oil obtained from PET based MLP experiments contains high fractions of medium and heavier range hydrocarbons (C11 – C20, C21 – C30). Sulfur content in the oil from different MLPs was measured as below the detection limit. Functional groups of hydrocarbons of oil were analyzed using FT-IR. Solids were characterized for the presence of heavy metals such as Al, Cr, Cu, Co, Pd, and Ni. © 2020 Institution of Chemical Engineers

Department Of Civil Engineering

World University root node

Department of Electrical Engineering

Department of Mathematics

Process Safety and Environmental Protection

Catalytic pyrolysis of polyoleﬁn and multilayer packaging based waste plastics: A pilot scale study

On-chip low skew clock distribution driving large load capacitances can consume as much as 70% of the total dynamic power that is lost as heat, resulting in high cooling costs. To mitigate this, an energy recovering reconfigurable series resonance solution with all the critical support circuitry is described. This LC resonant clock driver on a 22 nm process node saves about 50% driver power (>40% overall) and has 50% less skew than non-resonant driver at 2 GHz, while operating down to 0.2 GHz for dynamic voltage and frequency scaling. Reconfiguring for pulse mode operation enables further power saving, using latches instead of flip-flop banks, for double data rate applications. Tradeoffs in timing performance versus power, based on theoretical analysis, are compared and verified, to enable synthesis of an optimal topology for a given application. © 2015 IEEE.

IEEE Transactions on Circuits and Systems I: Regular Papers

An Energy-Recovering Reconfigurable Series Resonant Clocking Scheme for Wide Frequency Operation

High speed dynamic logic implementations have power consumption bottlenecks when driving large capacitive loads that occur in clock trees, memory bit/word lines and I/O pads. This severely limits their use in a System on Chip (SoC) at Gigabit rates. A novel dynamic logic gate that saves switching power by 50% with LC resonance is described. The stored energy on the load capacitance is transferred using an inductor during logic evaluation and recovered back for pre-charge, rather than being wasted. Implementation in a standard 90nm CMOS process illustrates feasibility with realistic on-chip inductors. Inductor values below 5nH are sufficient to operate at 1GHz speed driving 1pF of load while consuming less than 1.1mW of power from a 1.8V supply, thus breaking the f.CV2 barrier. The savings are realized over a wider range of frequency and less sensitive to LC variations than previously reported. © 2012 IEEE.

IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC

Low power SoCs with resonant dynamic logic using inductors for energy recovery

Driver circuits that save switching power by 25 % or more using LC resonance energy recovery are shown for use in clock and data networks. Resonant and other energy savings circuits are shown from global to local leaf cell clocking. A 10× operating frequency range with power reductions allows dynamic voltage and frequency scaling for power management. The resonance used only for the brief transition periods rather than the entire clock cycle and thus small on-chip inductors around 2 nH range are sufficient to support this timing. A new resonant driver that generates tracking pulses at each transition of clock for dual edge operation across scaled frequencies is proposed. The design is readily scaled from 90 to 45 nm in standard CMOS processes and beyond. It is robust with 50 % variation in component values for functionality and skew performance. The resulting power savings add up to 10’s of watts in high performance processors. Skew reductions are achieved without needing to increase the interconnect widths. A 40 % driver active area reduction is also achieved. The scheme is naturally compatible with dynamic logic allowing their increased use at lower power. © 2014, Springer Science+Business Media New York.

Analog Integrated Circuits and Signal Processing

Wide operating frequency resonant clock and data circuits for switching power reductions

Driver circuits that save global clock and data switching power by 25% or more using LC resonance for energy recovery are shown. A 10x operating frequency range with power reductions allows dynamic voltage and frequency scaling for power management. The resonance operation is used only for the brief transition periods rather than the entire clock cycle and thus small on-chip inductors around 2nH range are sufficient. The design is readily scaled from 90nm to 45nm in standard CMOS processes and is robust with 50% variation in component values. The resulting power savings add up to 10's of watts in high performance processors. © 2013 IEEE.

2013 IEEE 4th Latin American Symposium on Circuits and Systems, LASCAS 2013 - Conference Proceedings

Low power low voltage wide frequency resonant clock and data circuits for power reductions

A low-sensitivity temperature-compensated programmable BJT current-mode low-voltage filtering technique is proposed. We introduce a new technique in which the dc gain and the location of the second pole of the integrator are controlled such that the Q-enhancement, due to the second pole, is canceled by the effect of finite dc gain. The technique is suitable for integration and can work with low-value capacitors. By making the filter time constant exactly proportional to reC, good linear tunability is achieved over many decades. The programming current is varied as proportional to absolute temperature (PTAT) to stabilize the time constant reC. © 1999 IEEE.

IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications

A low-sensitivity programmable BJT current-mode filtering technique

Gaussian pulse shaping is used in digital communication systems like DECT, GSM, WLAN to minimize the out of band spectral energy. The baseband rectangular pulse stream is passed through a filter with a Gaussian impulse response before frequency modulating the carrier. Traditionally this is done by storing the values of the pulse shape in a ROM and converting it to an analog waveform with a DAC followed by a smoothing filter. This paper explores a fully analog implementation of an integrated Gaussian pulse shaper, which can result in a reduced power consumption and chip area.

Proceedings - IEEE International Symposium on Circuits and Systems

Baseband pulse shaping filter for Gaussian minimum shift keying

This paper describes a wireless local loop system under development, based on the DECT air interface standard. The key features of DECT, in particular the use of dynamic channel selection, are described. Propogation measurements that indicate the typical spacing of base stations are reported. A WLL-PSTN interconnect architecture is proposed, and simulation results indicating its capacity are presented.

IEEE International Conference on Personal Wireless Communications

DECT-based wireless local loop system

A revised model of the inflationary universe under the framework of Brans-Dicke theory is proposed. It is shown that the scale factor of the universe during the inflation varies as R approximately tw+1/2 and not exponentially, but still it gives rise to enough inflation to solve the cosmological puzzles. It is found that the quantum gravity effects come into play in the same scale as that of grand unified theories (i.e. at T approximately 1014 GeV) rather than at T approximately 10 19 GeV, hence providing a natural solution to the 'milder version' of the flatness problem inherent in the conventional inflationary scenarios. This scenario also provides a simple way to estimate theoretically the present value of the gravitational constant. The estimated value agrees well with the actual value despite many approximations and the ignorance of quantum gravity; the difference is only by a factor of the order of 10-2.