Driver circuits that save global clock and data switching power by 25% or more using LC resonance for energy recovery are shown. A 10x operating frequency range with power reductions allows dynamic voltage and frequency scaling for power management. The resonance operation is used only for the brief transition periods rather than the entire clock cycle and thus small on-chip inductors around 2nH range are sufficient. The design is readily scaled from 90nm to 45nm in standard CMOS processes and is robust with 50% variation in component values. The resulting power savings add up to 10's of watts in high performance processors. © 2013 IEEE.

C Mathiazhagan

Department of Electrical Engineering

DYNAMIC VOLTAGE AND FREQUENCY SCALING

HIGH PERFORMANCE PROCESSORS

LOW POWER LOW VOLTAGES

Onchip inductors

Operating frequency

Power managements

STANDARD CMOS PROCESS

TRANSITION PERIOD

Clocks

CMOS integrated circuits

Energy management

Low power electronics

IIT Madras is a public technical and research university located in Chennai, Tamil Nadu. Founded in 1959, it is recognised as an Institute of National Importance.

IIT Madras has been ranked as the top engineering institute in India for four years in a row by the National Institutional Ranking Framework of the MHRD

It currently offers undergraduate, postgraduate and research degrees across 16 disciplines in Engineering, Sciences, Humanities and Management. About 596 faculty belonging to science and engineering departments and centres of the Institute are engaged in teaching, research and industrial consultancy.

IIT Madras

Low power low voltage wide frequency resonant clock and data circuits for power reductions

2013 IEEE 4th Latin American Symposium on Circuits and Systems, LASCAS 2013 - Conference Proceedings

On-chip low skew clock distribution driving large load capacitances can consume as much as 70% of the total dynamic power that is lost as heat, resulting in high cooling costs. To mitigate this, an energy recovering reconfigurable series resonance solution with all the critical support circuitry is described. This LC resonant clock driver on a 22 nm process node saves about 50% driver power (>40% overall) and has 50% less skew than non-resonant driver at 2 GHz, while operating down to 0.2 GHz for dynamic voltage and frequency scaling. Reconfiguring for pulse mode operation enables further power saving, using latches instead of flip-flop banks, for double data rate applications. Tradeoffs in timing performance versus power, based on theoretical analysis, are compared and verified, to enable synthesis of an optimal topology for a given application. © 2015 IEEE.

IEEE Transactions on Circuits and Systems I: Regular Papers

An Energy-Recovering Reconfigurable Series Resonant Clocking Scheme for Wide Frequency Operation

Driver circuits that save switching power by 25 % or more using LC resonance energy recovery are shown for use in clock and data networks. Resonant and other energy savings circuits are shown from global to local leaf cell clocking. A 10× operating frequency range with power reductions allows dynamic voltage and frequency scaling for power management. The resonance used only for the brief transition periods rather than the entire clock cycle and thus small on-chip inductors around 2 nH range are sufficient to support this timing. A new resonant driver that generates tracking pulses at each transition of clock for dual edge operation across scaled frequencies is proposed. The design is readily scaled from 90 to 45 nm in standard CMOS processes and beyond. It is robust with 50 % variation in component values for functionality and skew performance. The resulting power savings add up to 10’s of watts in high performance processors. Skew reductions are achieved without needing to increase the interconnect widths. A 40 % driver active area reduction is also achieved. The scheme is naturally compatible with dynamic logic allowing their increased use at lower power. © 2014, Springer Science+Business Media New York.

Analog Integrated Circuits and Signal Processing

Wide operating frequency resonant clock and data circuits for switching power reductions

High speed dynamic logic implementations have power consumption bottlenecks when driving large capacitive loads that occur in clock trees, memory bit/word lines and I/O pads. This severely limits their use in a System on Chip (SoC) at Gigabit rates. A novel dynamic logic gate that saves switching power by 50% with LC resonance is described. The stored energy on the load capacitance is transferred using an inductor during logic evaluation and recovered back for pre-charge, rather than being wasted. Implementation in a standard 90nm CMOS process illustrates feasibility with realistic on-chip inductors. Inductor values below 5nH are sufficient to operate at 1GHz speed driving 1pF of load while consuming less than 1.1mW of power from a 1.8V supply, thus breaking the f.CV2 barrier. The savings are realized over a wider range of frequency and less sensitive to LC variations than previously reported. © 2012 IEEE.

20th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2012 - Proceedings

Low power SoCs with resonant dynamic logic using inductors for energy recovery

International Journal of Modern Trends in Engineering & Research

ACPI tool Implementation

2012 IEEE International Solid-State Circuits Conference

Resonant clock design for a power-efficient high-volume x86&#x2013;64 microprocessor

2011 IEEE International Symposium of Circuits and Systems (ISCAS)

Distributed LC resonant clock tree synthesis

IEEE Journal of Solid-State Circuits

A Resonant Global Clock Distribution for the Cell Broadband Engine Processor

Journal	2013 IEEE 4th Latin American Symposium on Circuits and Systems, LASCAS 2013 - Conference Proceedings
Open Access	No