Driver circuits that save switching power by 25 % or more using LC resonance energy recovery are shown for use in clock and data networks. Resonant and other energy savings circuits are shown from global to local leaf cell clocking. A 10× operating frequency range with power reductions allows dynamic voltage and frequency scaling for power management. The resonance used only for the brief transition periods rather than the entire clock cycle and thus small on-chip inductors around 2 nH range are sufficient to support this timing. A new resonant driver that generates tracking pulses at each transition of clock for dual edge operation across scaled frequencies is proposed. The design is readily scaled from 90 to 45 nm in standard CMOS processes and beyond. It is robust with 50 % variation in component values for functionality and skew performance. The resulting power savings add up to 10’s of watts in high performance processors. Skew reductions are achieved without needing to increase the interconnect widths. A 40 % driver active area reduction is also achieved. The scheme is naturally compatible with dynamic logic allowing their increased use at lower power. © 2014, Springer Science+Business Media New York.