Characterizing wide band continuous-time ΔΣ modulators is a challenge due to the high data rate at the output of the modulator. We propose the use of a duobinary test interface to extend the frequency range over which reliable laboratory measurements become possible. We show that using such an interface effectively randomizes the modulator output data and reduces high frequency content, thereby reducing the bandwidth demands made on the test equipment. Experimental results from a single-bit CTDSM operating at 4.4 GHz are given, demonstrating the efficacy of the technique. © 2013 IEEE.

Shanthi Pavan Y

Department of Electrical Engineering

Ankesh Jain

BANDWIDTH DEMAND

Continuous-time

Frequency contents

Frequency ranges

HIGH DATA RATE

LABORATORY MEASUREMENTS

OUTPUT DATA

TEST EQUIPMENTS

Continuous time systems

Equipment testing

MODULATORS

IIT Madras is a public technical and research university located in Chennai, Tamil Nadu. Founded in 1959, it is recognised as an Institute of National Importance.

IIT Madras has been ranked as the top engineering institute in India for four years in a row by the National Institutional Ranking Framework of the MHRD

It currently offers undergraduate, postgraduate and research degrees across 16 disciplines in Engineering, Sciences, Humanities and Management. About 596 faculty belonging to science and engineering departments and centres of the Institute are engaged in teaching, research and industrial consultancy.

IIT Madras

Improved characterization of high speed continuous-time ΔΣ modulators using a duobinary test interface

Proceedings - IEEE International Symposium on Circuits and Systems

Bench characterization of wide band oversampled converters is a challenge due to the high data rate at the output of the modulator. We propose the use of a duobinary test interface to extend the frequency range over which reliable laboratory measurements become possible. We show that using such an interface effectively randomizes the modulator output data and reduces high frequency content, thereby reducing the bandwidth demands made on the test equipment. It also reduces degradation of the modulator performance caused by package feedthrough effects. Experimental results from a test chip in 90 nm CMOS show that the proposed interface extends the upper sampling frequency limit of an existing single-bit CTDSM from 3.6 GHz to 4.4 GHz. © 2004-2012 IEEE.

IEEE Transactions on Circuits and Systems I: Regular Papers

Characterization techniques for high speed oversampled data converters

We give design considerations for single-bit continuous-time Delta-Sigma modulators (CTDSMs) with FIR feedback DACs. These modulators have the low jitter sensitivity and high linearity properties characteristic of a multibit modulator, while using a simple one-bit quantizer, thereby combining the advantages of single-bit and multibit operation. We propose a method to compensate the loop for the delay introduced by the FIR-DAC. The efficacy of our architectural and circuit techniques is borne out by measurement results from a modulator that achieves about 71-dB SNDR in a 36-MHz bandwidth while consuming only 15 mW from a 1.2-V supply. Implemented in a 90-nm CMOS process and sampling at 3.6 GS/s, the CTDSM has a figure of merit (FoM) of 72.7 fJ/lvl, while occupying 0.12 mm2. © 2012 IEEE.

IEEE Journal of Solid-State Circuits

Design techniques for wideband single-bit continuous-time ΔΣ modulators with FIR feedback DACs

We propose design techniques that enable the realization of power-efficient single-bit CT-ΔΣ ADCs at multi-Gb/s speeds. An FIR DAC [1] is used to reduce sensitivity to clock jitter and relax loop filter linearity. A mostly analog path compensates the modulator for the delay introduced by the FIR DAC. The CTDSM samples at 3.6GS/s, has 83dB DR in 36MHz BW, and occupies 0.12mm 2 in 90nm CMOS. Dissipating 15mW from a 1.2V supply, it thereby achieves an FoM SNDR of 72.8fJ/level, which is an improvement over the state of the art for converters with bandwidths greater than 20MHz. © 2012 IEEE.

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

A 15mW 3.6GS/s CT-ΔΣ ADC with 36MHz bandwidth and 83dB DR in 90nm CMOS

2012 IEEE International Solid-State Circuits Conference

A 20mW 61dB SNDR (60MHz BW) 1b 3rd-order continuous-time delta-sigma modulator clocked at 6GHz in 45nm CMOS

A 4 GHz Continuous-Time $DeltaSigma$ ADC With 70 dB DR and $-$74 dBFS THD in 125 MHz BW

IEEE Transactions on Communication and Electronics

The duobinary technique for high-speed data transmission

Journal	Data powered by TypesetProceedings - IEEE International Symposium on Circuits and Systems
Publisher	Data powered by TypesetInstitute of Electrical and Electronics Engineers Inc.
ISSN	02714310
Open Access	No