We present a simple, intuitive technique to compensate the loop filter transfer function for excess delay in low-pass continuous-time ΔΣ modulators. Conventional methods of finding the appropriate filter coefficients to account for loop delay work in the z-domain, leading to cumbersome algebra. We show that the same objective can be accomplished entirely in the continuous-time domain, resulting in a procedure that lends itself to hand calculations, even for high order modulators. We derive closed-form expressions for the loop filter coefficients in modulators using nonreturn-to-zero and return-to-zero digital-to-analog converters. Simulation results confirming the theory are given. © 2008 IEEE.

Shanthi Pavan Y

Department of Electrical Engineering

Analog to digital conversion

Continuous time systems

Delta sigma modulation

Digital signal processing

Digital to analog conversion

Frequency converters

functions

Hybrid computers

Multicarrier modulation

OPTICAL FREQUENCY CONVERSION

Analog-to-digital converter (ADC)

Compensation

Continuous-time

EXCESS DELAY

OVERSAMPLING

MODULATORS

IIT Madras is a public technical and research university located in Chennai, Tamil Nadu. Founded in 1959, it is recognised as an Institute of National Importance.

IIT Madras has been ranked as the top engineering institute in India for four years in a row by the National Institutional Ranking Framework of the MHRD

It currently offers undergraduate, postgraduate and research degrees across 16 disciplines in Engineering, Sciences, Humanities and Management. About 596 faculty belonging to science and engineering departments and centres of the Institute are engaged in teaching, research and industrial consultancy.

IIT Madras

Excess Loop Delay Compensation in Continuous-Time Delta-Sigma Modulators

IEEE Transactions on Circuits and Systems II: Express Briefs

Finite-impulse-response (FIR) feedback was originally introduced as a way to address the problem of loopfilter nonlinearity and clock jitter in continuous-time delta-sigma modulators. It turns out that FIR feedback has other benefits - it reduces the effect of the quantizer's data-dependent jitter and enables the use of chopping 'for free'. It is an architectural technique that combines the benefits of single-bit and multibit operation, and has proven itself to be robust and scalable, applicable to ΔΣ data converters targeting a variety of specifications, and across process nodes. This paper reviews the key challenges encountered in the design of high performance delta-sigma data converters, and describes the role of FIR feedback in addressing these challenges. The prospect of using FIR feedback to achieve wide bandwidths is examined, and promising directions are reviewed. © 2018 IEEE.

2018 IEEE Custom Integrated Circuits Conference, CICC 2018

Finite-impulse-response (FIR) feedback in continuous-time delta-sigma converters

Continuous-time ΔΣ modulators (CTDSM) used in wireless systems need to process signals in the presence of interferers. Peaking in the Signal Transfer Function of a conventional design necessitates a higher in-band dynamic range to accommodate interferers. A filter up front solves this problem at the expense of increased power dissipation and degraded linearity of the signal chain. Embedding the filter in the modulator achieves the same objective in a power efficient manner, while improving out-of-band linearity and reducing active area. However, having the filter inside a ΔΣ loop can be problematic with respect to stability. We show that such a system can be stabilized in a robust manner without extra hardware. Measurements of a CTDSM (signal BW = 2 MHz), with a built-in VGA (0 to 18 dB) and a second order Butterworth filter (4 MHz cutoff), show that the in-band/out-of-band IIP3 improves by about 3/10 dB when compared to the filter-CTDSM cascade, and achieves a similar dynamic range and consumes 25% lower power. © 1966-2012 IEEE.

IEEE Journal of Solid-State Circuits

Design techniques for continuous-time ΔΣ modulators with embedded active filtering

The maximum sampling rate of a continuous-time ΔΣ modulator is limited by quantizer delay. Most conventional delay compensation techniques address less than a clock cycle of delay. A technique previously proposed for compensating quantizer delays in excess of a clock cycle in bandpass modulators involves a parallel feedback path that bypasses the quantizer. We analyze this technique for low-pass modulators and show that sampling rates hitherto not possible can be achieved. Design tradeoffs are investigated, and simulation results showing the effectiveness of the technique are given. © 2010 IEEE.

Compensating for quantizer delay in excess of one clock cycle in continuous-time ΔΣ modulators

We present architectural and circuit details of a high speed continuous-time δσ modulator operating at a sampling rate of 300 Msps in a 0.18μm CMOS process. A large quantizer range of 2.4 V (peak-to-peak differential) reduces thermal noise requirements of the loop filter and matching requirements in the flash ADC. Active-RC techniques are used in the loop filter, and excess loop delay compensation circuitry mitigates the effect of finite bandwidth of the opamps and feedback DAC delay. Thanks to the design techniques employed, the modulator achieves a peak SNR of 67.2 dB in a 15 MHz bandwidth (OSR = 10) while dissipating 20.7 mW from a 1.8 V supply.©2009 Springer Science+Business Media, LLC.

Analog Integrated Circuits and Signal Processing

A power efficient continuous time δσ modulator with 15 MHz bandwidth and 70 dB dynamic range

We present design considerations for low-power continuous-time ΔΣ modulators. Circuit design details and measurement results for a 15 bit audio modulator are given. The converter, designed in a 0.18 μm CMOS technology, achieves a dynamic range of 93.5 dB in a 24 kHz bandwidth and dissipates 90 μW from a 1.8 V supply. It features a third-order active-RC loop filter, a very low-power 4-bit flash quantizer, and an efficient excess-delay compensation scheme to reduce power dissipation. © 2008 IEEE.

A power optimized continuous-time ΔΣ ADC for audio applications

Understanding Delta-Sigma Data Converters

A 20-mW 640-MHz CMOS Continuous-Time $SigmaDelta$ ADC With 20-MHz Signal Bandwidth, 80-dB Dynamic Range and 12-bit ENOB

A 32-mW 320-MHz Continuous-Time Complex Delta-Sigma ADC for Multi-Mode Wireless-LAN Receivers

A 70-mW 300-MHz CMOS continuous-time /spl Sigma//spl Delta/ ADC with 15-MHz bandwidth and 11 bits of resolution

Excess loop delay compensation in continuous-time delta-sigma modulators

Journal	Data powered by TypesetIEEE Transactions on Circuits and Systems II: Express Briefs
Publisher	Data powered by TypesetInstitute of Electrical and Electronics Engineers Inc.
ISSN	15497747
Open Access	No