Conventional continuous-time ΔΣ modulators that use non-return-to-zero (NRZ) feedback DACs suffer from distortion due to intersymbol interference (ISI) and are sensitive to clock jitter. Using a return-to-zero (RZ) DAC solves the problem of ISI, but exacerbates clock jitter sensitivity. The clock jitter sensitivity of an NRZ DAC can be reduced using a switched-capacitor (SC) DAC, but the large peak-to-average ratio of the DAC waveform degrades modulator linearity. In this work, we introduce the switched-capacitor return-to-zero (SCRZ) DAC, which combines the low clock jitter sensitivity of the SC DAC with the low distortion of an RZ DAC. The efficacy of the SCRZ principle is borne out by measurement results from a modulator that achieves a DR/SNR/SNDR of 87.1/84.5/82.3 dB in a 2 MHz bandwidth while dissipating 16.5 mW from a 1.8-V supply. The converter, designed in a 0.18-μ CMOS technology, reduces clock jitter sensitivity by 28 dB when compared with a traditional RZ DAC. © 1966-2012 IEEE.

Shanthi Pavan Y

Department of Electrical Engineering

Continuous-time

Over sampling

Quantization

Return-to-zero

SIGMA DELTA

Switched Capacitor

Analog to digital conversion

Capacitors

Clocks

CMOS integrated circuits

Continuous time systems

Digital integrated circuits

Intersymbol interference

Jitter

MODULATORS

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IIT Madras

Continuous-Time $\Delta \Sigma $ Modulators With Improved Linearity and Reduced Clock Jitter Sensitivity Using the Switched-Capacitor Return-to-Zero DAC

IEEE Journal of Solid-State Circuits

Many signal chains need to digitize signals in the presence of interferers. The usual way of accomplishing this is to use an analog anti-alias filter followed by a Nyquist ADC. Continuous-time ΔΣ<math xmlns="http://www.w3.org/1998/Math/MathML"><mi>Δ</mi><mi>Σ</mi></math>&nbsp;modulators (CTΔΣ<math xmlns="http://www.w3.org/1998/Math/MathML"><mi>Δ</mi><mi>Σ</mi></math>&nbsp;M) are compelling alternatives to Nyquist rate ADCs. While oversampling relaxes the requirements of the anti-alias filter, it is natural to wonder if the built-in filtering of a CTΔΣ<math xmlns="http://www.w3.org/1998/Math/MathML"><mi>Δ</mi><mi>Σ</mi></math>&nbsp;M, characterized by its Signal Transfer Function (STF), can be used to attenuate interferers so that an explicit filter up front can be dispensed with altogether. It turns out that the Signal Transfer Function (STF) of a conventional CTΔ ΣM is a by-product of NTF synthesis, with the designer having little control over it. The STF can be independently controlled by using a filter up front—however, this increases power dissipation and degrades linearity of the signal chain. Embedding the filter in the modulator achieves the same objective in a power efficient manner, while improving out-of-band linearity and reducing active area. This work reviews filtering ΔΣ<math xmlns="http://www.w3.org/1998/Math/MathML"><mi>Δ</mi><mi>Σ</mi></math>&nbsp;conversion and circuit techniques for such converters.

Wideband Continuous-time ΣΔ ADCs, Automotive Electronics, and Power Management: Advances in Analog Circuit Design 2016

Design considerations for filtering Delta Sigma converters

Single-bit continuous-time sigma-delta modulators (CTDSMs) are overly sensitive to clock jitter when a non-return-to-zero (NRZ) feedback DAC is used. One way of addressing this problem is to use a DAC with an exponentially decaying pulse shape, realized using a switched capacitor (SC). Existing variants of the SC feedback DAC degrade linearity due to the high peak-to-average ratio of the feedback waveform and severely compromise the alias rejection of the modulator around multiples of the sampling frequency. We introduce the dual switched-capacitor return-to-zero (Dual-SCRZ) DAC, which combines the low clock jitter sensitivity of a switched-capacitor DAC with the low peak-to-average ratio characteristic of NRZ feedback. Further, this DAC preserves the implicit anti-aliasing feature of the CTDSMs around all odd multiples of the sampling frequency. A single-bit CTDSMs that uses the Dual-SCRZ technique and opamp-assistance to improve linearity and reduce jitter sensitivity achieves 91/85.1/83 dB DR/SNR/SNDR in a 2 MHz bandwidth. Operating at 256 MHz in a 0.18 μm CMOS process, the modulator dissipates 14.8 mW from a 1.8 V supply. © 2016 IEEE.

Design of Continuous-Time ΔΣ Modulators with Dual Switched-Capacitor Return-to-Zero DACs

Single-bit continuous-time delta-sigma modulators (CTDSM) using FIR feedback DACs inherit the appealing aspects of both single-bit and multibit designs, without the disadvantage of either approaches. In this work, we give a method for stabilizing a CTDSM that uses an FIR feedback DAC. Further, we show that increasing the number of taps beyond a certain number (dependent on the architecture and oversampling ratio of the modulator) does not improve performance. The results of our analysis are incorporated in the design of a third-order audio CTDSM which achieves a peak A-weighted SNR of 102.3 dB (raw SNR of 98.9 dB) and a spurious-free dynamic range of 106 dB in a 24 kHz bandwidth, while consuming only 280 μW from a 1.8 V supply. © 1966-2012 IEEE.

Low power design techniques for single-bit audio continuous-time delta sigma ADCs using FIR feedback

An optimally designed FIR feedback DAC is used in a third order, single bit continuous-time delta sigma modulator to reduce power dissipation and jitter sensitivity. The loop filter is carefully stabilized for the delay added by the FIR DAC. A current reuse two stage feedforward compensated opamp minimizes current consumption in the first integrator. The efficacy of our techniques is borne out by measurements from a 17 bit audio converter designed in a 0.18 μm CMOS technology. It achieves 103 dB dynamic range, 102 dB A-Weighted SNR and 106 dB SFDR in a 24 kHz bandwidth and dissipates 280 μW from a 1.8 V supply. © 2013 IEEE.

Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013

A 280μW audio continuous-time ΔΣ modulator with 103dB DR and 102dB A-Weighted SNR

We give design considerations for single-bit continuous-time Delta-Sigma modulators (CTDSMs) with FIR feedback DACs. These modulators have the low jitter sensitivity and high linearity properties characteristic of a multibit modulator, while using a simple one-bit quantizer, thereby combining the advantages of single-bit and multibit operation. We propose a method to compensate the loop for the delay introduced by the FIR-DAC. The efficacy of our architectural and circuit techniques is borne out by measurement results from a modulator that achieves about 71-dB SNDR in a 36-MHz bandwidth while consuming only 15 mW from a 1.2-V supply. Implemented in a 90-nm CMOS process and sampling at 3.6 GS/s, the CTDSM has a figure of merit (FoM) of 72.7 fJ/lvl, while occupying 0.12 mm2. © 2012 IEEE.

Design techniques for wideband single-bit continuous-time ΔΣ modulators with FIR feedback DACs

We introduce the Switched-Capacitor Return-to-Zero (SCRZ) DAC, which combines the low clock jitter sensitivity of a Switched-Capacitor DAC with the low distortion of a Return-to-Zero DAC. A single-bit continuous-time ΔΣ modulator that uses the SCRZ technique and opamp-assistance to improve DAC linearity and reduce jitter sensitivity achieves 87.1/84.5/82.3 dB DR/SNR/SNDR in a 2 MHz bandwidth. Operating at a sampling rate of 256 MHz in a 0.18 μm CMOS process, the CTDSM dissipates 16.5 mW from a 1.8 V supply. © 2012 IEEE.

Proceedings of the Custom Integrated Circuits Conference

A continuous-time ΔΣ modulator with 87 dB dynamic range in a 2MHz signal bandwidth using a switched-capacitor return-to-zero DAC

We propose a technique that enables the study of weak loop filter nonlinearities in a class of continuous-time delta-sigma modulators. The technique can easily be implemented in a tool intended to simulate discrete-time modulators with linear loop filters, thereby significantly reducing the simulation time. Thanks to this technique, the utility of the Schreier Delta-Sigma toolbox can be extended to include weakly nonlinear effects in the loop filter, thus enabling the architectural exploration of alternate loop filter and operational amplifier (opamp) topologies. The results from the use of our technique are compared to those obtained using a circuit simulator, and good agreement is seen. © 2006 IEEE.

IEEE Transactions on Circuits and Systems I: Regular Papers

Efficient simulation of weak nonlinearities in continuous-time oversampling converters

The opamp in the first integrator of a high resolution single-bit continuous-time ΔΣ modulator has stringent slew rate requirements, which increases power dissipation. We introduce the assisted opamp integrator, which is a way of achieving low distortion operation with low power consumption. We present circuit implementations of our technique for single-bit modulators using NRZ and switched-capacitor-resistor (SCR) feedback DACs. Audio modulators designed in a 0.18 μm CMOS technology are used as vehicles to demonstrate the effectiveness of our techniques. The modulator with an NRZ DAC achieves a dynamic range of 92.5 dB in a 24 kHz bandwidth and dissipates 110 μW from a 1.8 V supply. A second design, which employs an SCR-DAC, achieves a dynamic range of 91.5 dB and dissipates 122 μW. The figures of merit (FOM) of these modulators, 175.9 dB and 174.4 dB respectively, are comparable with those of state-of-the-art multibit designs. © 2010 IEEE.

Power reduction in continuous-time delta-sigma modulators using the assisted opamp technique

We address the practical problem of determining the loop filter component values in a single-loop continuous-time delta sigma modulator. Conventional techniques to design center the converter to achieve a desired noise transfer function are cumbersome and not numerically stable. We present a robust procedure that can be used to determine the loop filter coefficients when real opamps (with finite gain, arbitrary Digital to Analog Converter (DAC) pulse, and multiple internal poles/zeros) are used. The method can also account for excess loop delay. We illustrate our technique with second-order low-pass and fourth-order bandpass examples. © 2010 IEEE.

Journal	Data powered by TypesetIEEE Journal of Solid-State Circuits
Publisher	Data powered by TypesetInstitute of Electrical and Electronics Engineers Inc.
ISSN	00189200
Open Access	No