One of the most flexible and modular approaches to reconfigurable systems is a bus-based approach. In order to get realistic performance estimates of these systems, detailed modeling of the processor as well as the bus and memory hierarchy is required. In addition, when coupling one or more reconfigurable units with a superscalar, out-of-order issue, load/store RISC CPU using the on-chip system bus, there are issues relating to cache coherency that need to be addressed. We have developed a cycle accurate co-simulator that uses a 'C' model of the processor and HDL models of the bus and reconfigurable units. We have also made modifications to the CPU pipeline to allow for non-cacheable accesses to the reconfigurable unit. This is reported in the paper. We have used this simulator to look at (a) The speedup obtained for two examples, namely, matrix multiplication and Lempel-Ziv compression, (b) the speedup obtained when there is a context switch from one application to the other and full reconfiguration is employed and (c) speedup obtained with partial reconfiguration. These results are reported in the paper. © 2004 Elsevier B.V. All rights reserved.

Vinita Vasudevan

Department of Electrical Engineering

Computer simulation

Computer software

Data storage equipment

Field programmable gate arrays

Microprocessor chips

Pipeline processing systems

REDUCED INSTRUCTION SET COMPUTING

BUS BASED SYSTEMS

Co-simulation

EMBEDDED FPGA

reconfiguration

SYSTEM ON A CHIP (SOC)

Embedded systems

Fulltext

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IIT Madras

Microprocessors and Microsystems

Reconfigurable hybrid processor systems provide a flexible platform for mapping data-parallel applications, while providing considerable speedup over software implementations. However, the overhead for reconfiguration presents a significant deterrent in mapping applications onto reconfigurable hardware. Partial runtime reconfiguration is one approach to reduce the reconfiguration overhead. In this paper, we present a methodology to map data-parallel tasks onto hardware that supports partial reconfiguration. The aim is to obtain the maximum possible speedup, for a given reconfiguration time, bus speed, and computation speed. The proposed approach involves using multiple, identical but independent processing units in the reconfigurable hardware. Under nonzero reconfiguration overhead, we show that there exists an upper limit on the number of processing units that can be employed beyond which further reduction in execution time is not possible. We obtain solutions for the minimum processing time, the corresponding load distribution, and schedule for data transfer. To demonstrate the applicability of the analysis, we present the following: 1) various plots showing the variation of processing time with different parameters; 2) hardware simulations for two examples, viz., 1-D discrete wavelet transform and finite impulse response filter, targeted to Xilinx field-programmable gate arrays (FPGAs); and 3) experimental results for a hardware prototype implemented on a FPGA board. © 2006 IEEE.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Mapping data-parallel tasks onto partially reconfigurable hybrid processor architectures

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A reconfigurable system featuring dynamically extensible embedded microprocessor, FPGA, and customizable I/O

Journal	Microprocessors and Microsystems
ISSN	01419331
Open Access	No