A driver amplifier suitable for integration with an 18 bit 500 kS/s successive approximation register analog-to-digital converter (ADC) is reported. It accepts single-ended or fully differential inputs. The driver consumes 12.5 mW from a 5 V supply, has a -115 dB (-120 dB) total harmonic distortion for 8 Vppd output at 1 kHz (10 kHz), a 240 ns settling time to 0.01% accuracy for a 2 Vppd output step, and an input-referred noise of 11.1 nV/√Hz. Simulated 18 bit settling time is 900 ns, and σ input-referred offset is 1.2 mV. This is one of the first reported 18 bit CMOS ADC driver amplifiers, and its performance is comparable to that of the state-of-the-art parts in other processes. © 2015 IEEE.

Nagendra Krishnapura

Department of Electrical Engineering

Amplifiers (electronic)

Approximation theory

CMOS integrated circuits

Frequency converters

Analog to digital converters

DRIVER AMPLIFIER

Fully differential

INPUT DRIVER

State of the art

SUCCESSIVE APPROXIMATION REGISTER

SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER

Total harmonic distortion (THD)

Analog to digital conversion

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IIT Madras

A 12.5 mW, 11.1 $\text{nV}/\sqrt{\text{Hz}}$ , −115 dB THD, $ Settling, 18 bit SAR ADC Driver in 0.6 $\mu\text{m}$ CMOS

IEEE Transactions on Circuits and Systems II: Express Briefs

Low distortion filters and oscillators that are useful for testing high-resolution ADCs are demonstrated in a 0.6 μm CMOS process. Band-pass filter prototypes with center frequencies of 1 and 10 kHz have 60 dB attenuation at the second harmonic, THD &lt; -115 dBc while driving 10 Vppd output, and 44 μV rms output noise. The oscillator prototype can generate 1 or 10 kHz and has THD &lt; -115 dBc while driving 8 Vppd output. Distortion generation mechanisms in the filter and oscillator are analyzed. The nonlinearity of the output stage of the opamp used in the active filter coupled with the capacitance at the input of that stage is shown to be the main cause of nonlinearity. This is suppressed using a buffer between the first and the second stage of the opamp. The modulation of the oscillator's loss due to ripple in the output of the amplitude stabilization loop that is required for stable sinusoidal oscillations turns out to be a significant contributor to distortion. A four-phase full-wave rectifier combined with second-order ripple filtering minimizes this effect. The filters occupy 11mm2 and consume 65 mW from 5.6 V. The oscillator occupies 8.5 mm2 and consumes 50 mW from 5 V. Measured frequency and amplitude stability over 166 min are 0.95 mHz (17.3 mHz) and 91 μV (45 μ V) at 1 kHz (10 kHz). © 2004-2012 IEEE.

IEEE Transactions on Circuits and Systems I: Regular Papers

Design considerations for low-distortion filter and oscillator ICs for testing high-resolution ADCs

A 12.5 mW, 11.1 nV/√Hz, -115 dB THD, < 1 μs Settling, 18 bit SAR ADC Driver in 0.6 μm CMOS

A 0.0045- <inline-formula> <tex-math notation="TeX">$hbox{mm}^{2}$</tex-math></inline-formula> 32.4- <inline-formula> <tex-math notation="TeX">$muhbox{W} $</tex-math></inline-formula> Two-Stage Amplifier for pF-to-nF Load Using CM Frequency Compensation

Analog Circuit Design

Driving lessons for a low noise, low distortion, 16-bit, 1Msps SAR ADC

IEEE Journal of Solid-State Circuits

A 0.016-mm$^{2}$ 144-$mu$W Three-Stage Amplifier Capable of Driving 1-to-15 nF Capacitive Load With $> $0.95-MHz GBW

Application and optimization of a 2GHz differential amplifier/ADC driver

Journal	Data powered by TypesetIEEE Transactions on Circuits and Systems II: Express Briefs
Publisher	Data powered by TypesetInstitute of Electrical and Electronics Engineers Inc.
ISSN	15497747
Open Access	No