We investigate the breakdown (V br) enhancement potential of the field plate (FP) technique in the context of AlGaN/GaN power HEMTs. A comprehensive account of the critical geometrical and material variables controlling the field distribution under the FP is provided. A systematic procedure is given for designing a FP device, using two-dimensional (2-D) simulation, to obtain the maximum V br with minimum degradation in on-resistance and frequency response. It is found that significantly higher V br can be achieved by raising the dielectric constant (ε i) of the insulator beneath the FP. Simulation gave the following estimates. The FP can improve the V br by a factor of 2.8-5.1, depending on the 2-DEG concentration (n s) and ε i. For n s = 1 × 10 13/cm 2, the V br can be raised from 123 V to 630 V, using a 2.2 μm FP on a 0.8 μm silicon nitride, and 4.7 μm gate-drain separation. The methodology of this paper can be extended to the design of FP structures in other lateral FETs, such as MESFETs and LD-MOSFETs.

Shreepad Karmalkar

Department of Electrical Engineering

Aluminum gallium nitride

FIELD PLATE DEVICE

Computer simulation

Electric breakdown

Electric insulators

Electric resistance

MESFET devices

MOSFET devices

Permittivity

SEMICONDUCTING ALUMINUM COMPOUNDS

SEMICONDUCTING GALLIUM COMPOUNDS

Semiconductor device models

Semiconductor device structures

high electron mobility transistors

IIT Madras is a public technical and research university located in Chennai, Tamil Nadu. Founded in 1959, it is recognised as an Institute of National Importance.

IIT Madras has been ranked as the top engineering institute in India for four years in a row by the National Institutional Ranking Framework of the MHRD

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IIT Madras

Enhancement of breakdown voltage in AlGaN/GaN high electron mobility transistors using a field plate

IEEE Transactions on Electron Devices

We studied AlGaN/GaN high electron mobility transistors grown on a SiC substrate. They had a hard breakdown voltage V BR ≥ 70 V under a deep OFF-state with a much less and softer V BR ∼ 27 V for near-threshold OFF-state gate bias conditions. We established that the low, soft breakdown is due to space charge limited current (SCLC) from drain to source via the GaN buffer, which has deep traps. Previous works had established the presence of SCLC from bulk to gate and drain to gate. For the first time we establish drain to source SCLC. We achieved this by analyzing the I DS-V DS data extracted from the measured I S-V DS. We determined the following by numerical simulation: (a) the density and energy level of traps causing the observed SCLC; (b) the minimum trap density required to suppress the SCLC and raise the V BR up to the avalanche limit for the whole OFF-state regime for devices with a channel length down to 0.15 μm. © 2019 The Japan Society of Applied Physics.

Fulltext

Japanese Journal of Applied Physics

Mechanism and enhancement of the near-threshold low OFF-state breakdown voltage in gallium nitride high electron mobility transistors

This paper reports on the analytical approach for designing field plates for reducing the electric field in the channel and at the surface of heterostructure field-effect transistors (HFETs) for a given drain voltage, with the smallest possible increase of the gate capacitance. The analytical calculations for GaN-based HFETs are in good agreement with the two-dimensional numerical simulations. © 2005 IEEE.

Field-plate engineering for HFETs

A novel HEMT configuration based on the RESURF technique is proposed for very high voltage power switching applications. It employs a p-n junction below the 2-DEG channel and two field plates, one extending from the gate and the other from the drain, to distribute the electric field over the gate to drain separation. 2-D simulations indicate a breakdown voltage &gt; 1 KV at on-resistance of ∼1 mΩ-cm2 (neglecting contact resistances) for the device.

IEEE Electron Device Letters

RESURF AlGaN/GaN HEMT for high voltage power switching

We investigate a technique that has the potential to enhance the breakdown voltage (Vbr) of AlGaN/GaN high electron mobility transistors (HEMTs) beyond 1 kV. The technique involves incorporation of a field plate (FP) connected to the gate and placed over a stepped insulator (SI). A comprehensive account of the critical geometrical and material variables controlling the field distribution under the FP is provided. A systematic procedure is given for designing a SIFP device, using 2-D simulation, to obtain the maximum Vbr with minimum degradation in on-resistance and frequency response. Simulations show that, for a 2-DEG concentration of 1 × 1013cm-2, the maximum Vbr achievable with a stepped aluminum nitride (silicon nitride) insulator can be 2.6 (2.3) times higher than that with a uniform insulator; Vbr∼1 kV can be obtained using a gate to drain separation as low as ∼7 μm. The methodology of this paper can be extended to t he design of SIFP structures in other lateral FETs, such as MESFETs and LD-MOSFETs.© 2001 Elsevier Science Ltd. All rights reserved.

Solid-State Electronics

Very high voltage AlGaN/GaN high electron mobility transistors using a field plate deposited on a stepped insulator

High breakdown GaN HEMT with overlapping gate structure

Journal of Applied Physics

Analysis of electric field distribution in GaAs metal–semiconductor field effect transistor with a field-modulating plate

Experimental evaluation of impact ionization coefficients in GaN

High-power microwave GaN/AlGaN HEMTs on semi-insulating silicon carbide substrates

Journal	IEEE Transactions on Electron Devices
ISSN	00189383
Open Access	No