Get all the updates for this publication
Conferences
Efficient VLSI architectures for the Hadamard transform based on offset-binary coding and ROM decompositionPublished in
2011
Pages: 347 - 348
We present efficient architectures for the discrete Hadamard transform based on two techniques, namely offset binary coding and ROM decomposition. The proposed architectures do not require large size ROMs in comparison to a recently proposed solution. Results of FPGA implementation show that the solutions have a low slice-delay product. © 2011 IEEE.
Topics: Hadamard transform (62)%62% related to the paper, Very-large-scale integration (53)%53% related to the paper and Binary code (52)%52% related to the paper
View more info for "Efficient VLSI Architectures for the Hadamard Transform Based on Offset-Binary Coding and ROM Decomposition"
Content may be subject to copyright.
Related Papers (3)
ConferencesHardware-efficient velocity estimation of dynamic obstacles based on a novel radix-4 cordic and FPGA implementation2018 | Institute of Electrical and Electronics Engineers Inc.
About the journal
| Journal | Proceedings - 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011 |
|---|---|
| Open Access | No |
Authors (1)
Krishnamurthy Sridharan- A parallel algorithm, architecture and FPGA realization for high speed determination of the complete visibility graph for convex objects
- A comparative study on the performance of differently treated plain carbon steel gears
- Carbon nanotube FET-based low-delay and low-power multi-digit adder designs
- Hardware-efficient prediction-correction-based generalized-voronoi-diagram construction and FPGA implementation
Concepts (13)
BINARY CODING- DISCRETE HADAMARD TRANSFORM
- DISTRIBUTED ARITHMETIC
- Efficient architecture
- Fpga implementations
- Hadamard transforms
- Large sizes
- Proposed architectures
- SLICE-DELAY PRODUCT
- Vlsi architectures
- Binary codes
- Computer architecture
- Mathematical transformations
