Conventional manufacturing/system tests point to a set of logically equivalent faults and not the exact fault within a faulty component. In this paper, we show that during testing, measuring the current drawn by a faulty component aids in identifying the exact manifested fault within it. We propose to partition the chip's power grid based on the chip's component partitions, and dedicate a external supply pin to each component partition. In order to minimize the cost associated with the external measurement circuitry, we reuse the scan resources available within the flip-flop to repeatedly apply the desired test-pattern pair, so that the average current measured during the launch-to-capture window, is equal to the same over a long period of time. The proposed technique is validated by simulating the power-grid and the modified flip-flop using SPICE circuit simulator. The proposed technique, when applied to several component benchmark circuits, helped to localize almost all the logically equivalent faults. © 2016 IEEE.

Kamakoti Veezhinathan

Circuit simulation

Electric current measurement

Electric power transmission networks

Flip flop circuits

Reconfigurable hardware

AVERAGE CURRENTS

Benchmark circuit

Circuit simulators

Component faults

CONVENTIONAL MANUFACTURING

EQUIVALENT FAULTS

SWITCHING CURRENT MEASUREMENTS

Test Pattern

SPICE

IIT Madras is a public technical and research university located in Chennai, Tamil Nadu. Founded in 1959, it is recognised as an Institute of National Importance.

IIT Madras has been ranked as the top engineering institute in India for four years in a row by the National Institutional Ranking Framework of the MHRD

It currently offers undergraduate, postgraduate and research degrees across 16 disciplines in Engineering, Sciences, Humanities and Management. About 596 faculty belonging to science and engineering departments and centres of the Institute are engaged in teaching, research and industrial consultancy.

IIT Madras

Component fault localization using switching current measurements

Proceedings of the European Test Workshop

Scan-based testing is crucial to ensuring correct functioning of chips. In this scheme, the scan and capture phases are interleaved. It is well known that for large designs, excessive switching activity during the launch-to-capture window leads to high voltage droop on the power grid, ultimately resulting in false delay failures during at-speed test. This article proposes a new design-for-testability (DFT) scheme for launch-onshift (LOS) testing, which ensures that the combinational logic remains undisturbed between the interleaved capture phases, providing computer-aided-design (CAD) tools with extra search space for minimizing launchto-capture switching activity through test pattern ordering (TPO). We further propose a new TPO algorithm that keeps track of the don't cares during the ordering process, so that the don't care filling step after the ordering process yields a better reduction in launch-to-capture switching activity compared to any other technique in the literature. The proposed DFT-assisted technique, when applied to circuits in ITC99 benchmark suite, produces an average reduction of 17.68% in peak launch-to-capture switching activity (CSA) compared to the best known lowpower TPO technique. Even for circuits whose test cubes are not rich in don't care bits, the proposed technique produces an average reduction of 15% in peak CSA, while for the circuits with test cubes rich in don't care bits (≥75%), the average reduction is 24%. The proposed technique also reduces the average power dissipation (considering both scan cells and combinational logic) during the scan phase by about 43.5% on an average, compared to the adjacent filling technique. © 2015 ACM.

ACM Transactions on Design Automation of Electronic Systems

DFT assisted techniques for peak launch-to-capture power reduction during launch-on-shift at-speed testing

Journal	Data powered by TypesetProceedings of the European Test Workshop
Publisher	Data powered by TypesetInstitute of Electrical and Electronics Engineers Inc.
ISSN	15301877
Open Access	No