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A parallel algorithm for constructing reduced visibility graph and its FPGA implementation
Published in
2004
Volume: 50
   
Issue: 10
Pages: 635 - 644
Abstract
A central geometric structure in applications such as robotic path planning and hidden line elimination in computer graphics is the visibility graph. A new parallel algorithm to construct the reduced visibility graph in a convex polygonal environment is presented in this paper. The computational complexity is O(p2log(n/p)) where p is the number of objects and n is the total number of vertices. A key feature of the algorithm is that it supports easy mapping to hardware. The algorithm has been simulated (and verified) using C. Results of hardware implementation show that the design operates at high speed requiring only small space. In particular, the hardware implementation operates at approximately 53 MHz and accommodates the reduced visibility graph of an environment with 80 vertices in one XCV3200E device. © 2004 Elsevier B.V. All rights reserved.
About the journal
JournalJournal of Systems Architecture
ISSN13837621
Open AccessNo
Concepts (18)
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    Fpga implementation
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    PARALLEL ALGORITHM AND ARCHITECTURE
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    REDUCED VISIBILITY GRAPH
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    ROBOTIC PLANNING
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    Computational complexity
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    Computer graphics
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    Computer hardware
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    Computer simulation
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    Field programmable gate arrays
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    Logic design
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    Motion planning
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    Personal computers
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    Program processors
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    Robotics
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    Set theory
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    Visibility
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    Vlsi circuits
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    Parallel algorithms