This paper proposes an analog-assisted digital output capacitor-less low-drop out (LDO) regulator. At full load, the digital loop supplies greater than 90% of the load whereas the rest is supplied by the analog loop. The analog loop regulates the output accurately eliminating the limit cycle oscillations and quantization error due to a standalone digital LDO. The analog loop is implemented with a flipped source follower architecture to achieve lower output impedance and higher bandwidth.. The digital loop employs 32-bit shift register to control the discrete set of power-FETs. A fast clock (250 MHz) is used to speed up the digital loop during load transients and a slower clock (10 MHz) is used in steady state for power saving. The LDO uses only 1pF as output capacitor and consumes a quiescent current of 17.3µA. The proposed LDO was implemented in TSMC-65nm for an input of 1.2V, output of 1V and achieves settling time less than 110ns with undershoot/overshoot of 24mV/72mV for 0.1-10mA/100ns load step. © 2020 IEEE