This paper describes a new Built-In-Self-Test(BIST) scheme for estimation of static non-linearity errors in digital to analog converters (DACs). The BIST scheme measures each transition and estimates non-linearity errors. It makes use of a sample and subtract circuit and a VCO. The circuit is designed using 0.35μm CMOS technology from AMS. The simulation results are included in this paper. Errors estimated using the BIST scheme simulation match well with measured errors.