CTDSMs operated in the incremental mode can achieve sample-by-sample conversion in a power efficient manner, while relaxing the requirements of the buffer driving the ADC. This work gives simple expressions for quantization and thermal noise of an incremental CTDSM. These are used to design a two channel incremental CTDSM that achieves a bandwidth of 6 6 kHz/channel. The ADC, designed in a 180nm CMOS process, achieves 85.1dB SNDR while consuming 55uW/channel from a 1.8 V supply. © 2016 IEEE.

Shanthi Pavan Y

Department of Electrical Engineering

Kamlesh Singh

CMOS integrated circuits

Continuous time systems

Data acquisition

Embedded systems

MODULATORS

analysis

delta

Incremental

Multichannel

Noise

Nyquist

OVERSAMPLED

SIGMA

Delta sigma modulation

IIT Madras is a public technical and research university located in Chennai, Tamil Nadu. Founded in 1959, it is recognised as an Institute of National Importance.

IIT Madras has been ranked as the top engineering institute in India for four years in a row by the National Institutional Ranking Framework of the MHRD

It currently offers undergraduate, postgraduate and research degrees across 16 disciplines in Engineering, Sciences, Humanities and Management. About 596 faculty belonging to science and engineering departments and centres of the Institute are engaged in teaching, research and industrial consultancy.

IIT Madras

A 14 Bit Dual Channel Incremental Continuous-Time Delta Sigma Modulator for Multiplexed Data Acquisition

Proceedings of the IEEE International Conference on VLSI Design

This paper presents new techniques to obtain sample-by-sample analog-to-digital conversion using a delta-sigma modulator (DSM) without resetting the modulator or the decimation filter. It is shown that memoryless A/D conversion without reset can be realized using a discrete-time DSM with a signal transfer function (STF) of unity and a Nyquist M -band decimation filter running at the oversampled rate. It is also shown that a delta-sigma ADC preceded by a sample-and-hold at the Nyquist rate is a linear, time-invariant system at the Nyquist rate. This relaxes the constraint on the STF and allows using a multi-rate decimation filter and an equalizer at the Nyquist rate to significantly lower the power in the digital filters. Crosstalk suppression, which is limited by analog imperfections when a fixed-coefficient equalizer is used, is shown to be substantially improved using an adaptive equalizer at the Nyquist rate. A 180-nm prototype operating at 32 MHz and an OSR of 32 demonstrates two-channel operation with crosstalk below 89 dB. It consumes 18.2 mA from a 1.8-V supply, occupies 3.86 mm2 and has DR/SNR/SNDR of 84.2/82.5/80.1 dB. © 2004-2012 IEEE.

IEEE Transactions on Circuits and Systems I: Regular Papers

Reset-free memoryless delta-sigma analog-to-digital conversion

The opamp in the first integrator of a high resolution single-bit continuous-time ΔΣ modulator has stringent slew rate requirements, which increases power dissipation. We introduce the assisted opamp integrator, which is a way of achieving low distortion operation with low power consumption. We present circuit implementations of our technique for single-bit modulators using NRZ and switched-capacitor-resistor (SCR) feedback DACs. Audio modulators designed in a 0.18 μm CMOS technology are used as vehicles to demonstrate the effectiveness of our techniques. The modulator with an NRZ DAC achieves a dynamic range of 92.5 dB in a 24 kHz bandwidth and dissipates 110 μW from a 1.8 V supply. A second design, which employs an SCR-DAC, achieves a dynamic range of 91.5 dB and dissipates 122 μW. The figures of merit (FOM) of these modulators, 175.9 dB and 174.4 dB respectively, are comparable with those of state-of-the-art multibit designs. © 2010 IEEE.

IEEE Journal of Solid-State Circuits

Power reduction in continuous-time delta-sigma modulators using the assisted opamp technique

2013 Proceedings of the ESSCIRC (ESSCIRC)

A 105-dB SNDR, 10 kSps multi-level second-order incremental converter with smart-DEM consuming 280 &#x00B5;W and 3.3-V supply

A Low-Power CT Incremental 3rd Order <formula formulatype="inline"> <tex Notation="TeX">$SigmaDelta$</tex></formula> ADC for Biosensor Applications

2012 IEEE International Symposium on Circuits and Systems

A 12-bit 7 &#x00B5;W/channel 1 kHz/channel incremental ADC for biosensor interface circuits

IEEE Custom Integrated Circuits Conference 2010

82 dB SNDR 20-channel incremental ADC with optimal decimation filter and digital correction

Journal	Data powered by TypesetProceedings of the IEEE International Conference on VLSI Design
Publisher	Data powered by TypesetIEEE Computer Society
ISSN	10639667
Open Access	No