Double Gate (DG) SOI MOSFETs offer several advantages over the conventional Single Gate (SG) SOI MOSFETs, viz. reduced short-channel effects and subthreshold swing as well as increased current drive and transconductance. However, DG MOSFETs require unconventional technology. In this paper, we show that it is possible to obtain virtual DG operation for both nMOSFETs and pMOSFETs in SOI CMOS technology using conventional SG SOI MOSFETs. The design has been carried out with the help of analytical formulation and subsequently verified using the 2-D Device Simulator MEDICI. © 2005 IEEE.

Amitava Dasgupta

Department of Electrical Engineering

Narasamma Lakshmi

Analytical formulation

HIGH-PERFORMANCE

subthreshold slope

Gates (transistor)

Silicon on insulator technology

Transconductance

MOSFET devices

IIT Madras is a public technical and research university located in Chennai, Tamil Nadu. Founded in 1959, it is recognised as an Institute of National Importance.

IIT Madras has been ranked as the top engineering institute in India for four years in a row by the National Institutional Ranking Framework of the MHRD

It currently offers undergraduate, postgraduate and research degrees across 16 disciplines in Engineering, Sciences, Humanities and Management. About 596 faculty belonging to science and engineering departments and centres of the Institute are engaged in teaching, research and industrial consultancy.

IIT Madras

Virtual Double-Gate Operation in Conventional SOI CMOS Technology

Proceedings of INDICON 2005: An International Conference of IEEE India Council

IEEE Transactions on Electron Devices

Correct biasing rules for virtual DG mode operation in SOI-MOSFETs

Silicon-on-Insulator Technology: Materials to VLSI

IEEE Electron Device Letters

An adjustable work function technology using Mo gate for CMOS devices

Microelectronics Reliability

State-of-the-art and future of silicon on insulator technologies, materials, and devices

Japanese Journal of Applied Physics

Buried Layer Engineering to Reduce the Drain-Induced Barrier Lowering of Sub-0.05 µm SOI-MOSFET

Virtual double-gate operation in conventional SOI CMOS technology

Journal	Proceedings of INDICON 2005: An International Conference of IEEE India Council
Open Access	No