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Synthesis of analog CMOS circuitsPublished in IEEE, Los Alamitos, CA, United States
1997
Pages: 439 - 444
In this paper we describe an efficient method for transistor sizing in cell level analog circuits. An equation based method is used. SPICE quality device models are used and the sizing problem is posed as an optimization problem. KCL, KVL and matching constraints are taken into account in the formulation of the optimization problem without explicitly introducing them as constraints as was done previously. A tool developed based on this method has been used to synthesize and study performance trade-offs in various CMOS op amps.
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About the journal
| Journal | Data powered by TypesetProceedings of the IEEE International Conference on VLSI Design |
|---|---|
| Publisher | Data powered by TypesetIEEE, Los Alamitos, CA, United States |
| Open Access | No |
Authors (1)
Vinita Vasudevan- A hierarchical technique for statistical path selection and criticality computation
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