This paper shows the hardware and the procedure utilized to test all components of the readout system (cables, FADC boards, junction boards) of the Belle II Silicon Vertex Detector after the series production. For the FADC board special testing hardware and firmware were designed and created to check all digital and analog inputs and outputs as well as all data interconnections on the board. The main FPGA on the FADC board generates digital signals which are converted to periodic analog differential alternating voltages up to 40 MHz on the FADC board tester, which then are fed into the analog inputs of the FADC board. Histograms and scans of the samples are recorded by using random equivalent-time sampling or sequential equivalent-time sampling, allowing to characterize the behavior of the system with a much higher bandwidth than the ADCs could do with conventional measurements. Small changes of parameters of the assembly (like using a cable of different length) lead to significant changes of the measured values, creating a sensitive testing instrument. The shapes of the distributions are analyzed and compared to references by software which then decides if a test is passed or not. The commissioning setup of the whole readout chain, with all the final components including the final detector, has been tested in three phases. The respective graphs of the signal-to-noise ratios of the strips of a detector module and histograms of the noise development of the whole detector show very high consistency of the SVD readout system. © 2019 Elsevier B.V.