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Router Buffer Caching for Managing Shared Cache Blocks in Tiled Multi-Core Processors
, Augustine J., , Jose J.
Published in Institute of Electrical and Electronics Engineers Inc.
Volume: 2020-October
Pages: 239 - 246
Multiple cores in a tiled multi-core processor are connected using a network-on-chip mechanism. All these cores share the last-level cache (LLC). For large-sized LLCs, generally, non-uniform cache architecture design is considered, where the LLC is split into multiple slices. Accessing highly shared cache blocks from an LLC slice by several cores simultaneously results in congestion at the LLC, which in turn increases the access latency. To deal with this issue, we propose a congestion management technique in the LLC that equips the NoC router with small storage to keep a copy of heavily shared cache blocks. To identify highly shared cache blocks, we also propose a prediction classifier in the LLC controller. We implement our technique in Sniper, an architectural simulator for multi-core systems, and evaluate its effectiveness by running a set of parallel benchmarks. Our experimental results show that the proposed technique is effective in reducing the LLC access time. © 2020 IEEE.
About the journal
JournalData powered by TypesetProceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
PublisherData powered by TypesetInstitute of Electrical and Electronics Engineers Inc.
Open AccessNo