Get all the updates for this publication
Conferences
Optimisation of the one-dimensional full search algorithm and implementation using an EPLDPublished in IEEE, Los Alamitos, CA, United States
2000
Pages: 336 - 341
This paper presents a technique for the modification and optimisation of the one-dimensional full search (IDFS) motion estimation algorithm. The modified version of the IDFS algorithm has desirable properties for efficient hardware implementation. The spatial redundancy between the motion vectors of the macroblocks within a frame is exploited for the purpose of optimisation. The performance of the proposed technique is competitive, as compared to the more popular hierarchical three step search (TSS) method. The speed of the proposed technique, when implemented in hardware, is higher than the TSS method. The results of an implementation in an EPLD, targeted for real time operation, are given.
Content may be subject to copyright.
Related Papers (3)
ConferencesGAS: GPU assisted process scheduling for multicore systems2018 | Association for Computing Machinery
About the journal
| Journal | Data powered by TypesetProceedings of the IEEE International Conference on VLSI Design |
|---|---|
| Publisher | Data powered by TypesetIEEE, Los Alamitos, CA, United States |
| Open Access | No |
Authors (1)
Vinita Vasudevan- A hierarchical technique for statistical path selection and criticality computation
- Analysis of clock jitter in continuous-time sigma-delta modulators
- A time-domain technique for computation of noise spectral density in switched capacitor circuits
- Simulation of the effects of timing jitter in track-and-hold and sample-and-hold circuits
Concepts (14)
Computer hardware- Hierarchical systems
- Microprocessor chips
- Motion compensation
- Optimization
- Performance
- Real time systems
- Vectors
- BLOCK MATCHING
- MACROBLOCKS
- Motion estimation
- Motion vectors
- THREE STEP SEARCH
- Algorithms
