Verifying equivalence of the behavioral specification and scheduled implementation is a significant problem in high-level synthesis, because scheduling changes the cycle-by-cycle behavior. The authors present a practical method for comparing simulation results for the two using the same vectors.

Salil Raje

Algorithms

Computational linguistics

Computer simulation

High level languages

Systems analysis

Vectors

High level synthesis

IMPLEMENTATION STATE

OBSERVABLE TIME WINDOWS

SPECIFICATION STATE

Computer hardware description languages

IIT Madras is a public technical and research university located in Chennai, Tamil Nadu. Founded in 1959, it is recognised as an Institute of National Importance.

IIT Madras has been ranked as the top engineering institute in India for four years in a row by the National Institutional Ranking Framework of the MHRD

It currently offers undergraduate, postgraduate and research degrees across 16 disciplines in Engineering, Sciences, Humanities and Management. About 596 faculty belonging to science and engineering departments and centres of the Institute are engaged in teaching, research and industrial consultancy.

IIT Madras

Observable time windows: verifying high-level synthesis results

IEEE Design and Test of Computers

Proceedings of the 32nd ACM/IEEE conference on Design automation conference - DAC '95

Behavioral synthesis methodology for HDL-based specification and validation

IBM Journal of Research and Development

High-level synthesis in an industrial environment

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

The Siemens high-level synthesis system CALLAS

A system for production use of high-level synthesis

Observable time windows: Verifying high-level synthesis results

Journal	IEEE Design and Test of Computers
ISSN	07407475
Open Access	No