The design of low-delay multibit adders in quantum dot cellular automata is considered in this brief. We present a general approach for delay reduction based on two new theorems called decomposition theorems. We consider the carry-lookahead adder (CLA) and the carry-flow adder (CFA) as specific applications of the theorems. For 16-bit CLA and 16-bit CFA, the decomposition theorems yield reductions in delay for the leading carry of approximately 60% and 25%, respectively, when compared to the best existing designs. In addition, the decomposition theorems lead to designs with low area-delay product. Simulations in QCADesigner are also presented. © 2012 IEEE.

Krishnamurthy Sridharan

Department of Electrical Engineering

CARRY LOOKAHEAD ADDER

CARRY-FLOW ADDER (CFA)

DECOMPOSITION THEOREMS

Delay

QUANTUM-DOT CELLULAR AUTOMATA

Design

Domain decomposition methods

MAJORITY LOGIC

Adders

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IIT Madras

New Decomposition Theorems on Majority Logic for Low-Delay Adder Designs in Quantum Dot Cellular Automata

IEEE Transactions on Circuits and Systems II: Express Briefs

The design of high-performance adders has experienced a renewed interest in the last few years; among high performance schemes, parallel prefix adders constitute an important class. They require a logarithmic number of stages and are typically realized using AND-OR logic; moreover with the emergence of new device technologies based on majority logic, new and improved adder designs are possible. However, the best existing majority gate-based prefix adder incurs a delay of 2log2 (η) 1 (due to the nth carry); this is only marginally better than a design using only AND-OR gates (the latter design has a 2log2 (η) 1 gate delay). This paper initially shows that this delay is caused by the output carry equation in majority gate-based adders that is still largely defined in terms of AND-OR gates. In this paper, two new majority gate-based recursive techniques are proposed. The first technique relies on a novel formulation of the majority gate-based equations in the used group generate and group propagate hardware; this results in a new definition for the output carry, thus reducing the delay. The second contribution of this manuscript utilizes recursive properties of majority gates (through a novel operator) to reduce the circuit complexity of prefix adder designs. Overall, the proposed techniques result in the calculation of the output carry of an n-bit adder with only a majority gate delay of log2 (η) 1. This leads to a reduction of 40percent in delay and 30percent in circuit complexity (in terms of the number of majority gates) for multi-bit addition in comparison to the best existing designs found in the technical literature. © 1968-2012 IEEE.

IEEE Transactions on Computers

Majority logic formulations for parallel adder designs at reduced delay and circuit complexity

Proceedings of the IEEE

Design Tools for an Emerging SoC Technology: Quantum-Dot Cellular Automata

Journal of the Franklin Institute

Quantum-dot devices and Quantum-dot Cellular Automata

Pipelined adders

Nanotechnology

Quantum cellular automata

New decomposition theorems on majority logic for low-delay adder designs in quantum dot cellular automata

Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
ISSN	15497747
Open Access	No