Interconnects have become the chief bottleneck in today's era of chip design. Along the road of interconnect evolution, Network-on-Chips (NoCs) have emerged as a structured and scalable solution for connecting computational elements on a very large scale integration chip. Also, with the deep-submicron technology allowing integration of billions of transistors, chips have grown very complex and large in size. The global wire-length problem was addressed with the integration of devices in the third dimension (3-D). The combination of 3-D integration and a scalable interconnect, like NoCs, promise to revolutionize design for Chip Multi-processors, System-on-chips, and System-in-package. This paper surveys on all the advancements in 3-D NoCs. Copyright © 2012 by the IETE.