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Network-on-chips on 3-D ICs: Past, present, and future
Kamakoti Veezhinathan
Published in
2012
Volume: 29
   
Issue: 4
Pages: 318 - 335
Abstract
Interconnects have become the chief bottleneck in today's era of chip design. Along the road of interconnect evolution, Network-on-Chips (NoCs) have emerged as a structured and scalable solution for connecting computational elements on a very large scale integration chip. Also, with the deep-submicron technology allowing integration of billions of transistors, chips have grown very complex and large in size. The global wire-length problem was addressed with the integration of devices in the third dimension (3-D). The combination of 3-D integration and a scalable interconnect, like NoCs, promise to revolutionize design for Chip Multi-processors, System-on-chips, and System-in-package. This paper surveys on all the advancements in 3-D NoCs. Copyright © 2012 by the IETE.
About the journal
JournalIETE Technical Review (Institution of Electronics and Telecommunication Engineers, India)
ISSN02564602
Open AccessNo
Concepts (17)
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    3-D ICS
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    3-D INTEGRATION
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    CHIP DESIGN
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    Computational elements
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    Deep sub-micron technology
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    Multi-processors
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    NETWORK-ON-CHIPS
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    SCALABLE SOLUTION
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    SYSTEM IN PACKAGE
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    System on chips
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    VERY LARGE SCALE INTEGRATION CHIPS
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    WIRE LENGTH
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    Integrated circuits
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    Integration
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    Optical interconnects
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    Timing jitter
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    Microprocessor chips