The design of adders on quantum dot cellular automata (QCA) has been of recent interest. While few designs exist, investigations on reduction of QCA primitives (majority gates and inverters) for various adders are limited. In this paper, we present a number of new results on majority logic. We use these results to present efficient QCA designs for the ripple carry adder (RCA) and various prefix adders. We derive bounds on the number of majority gates for n-bit RCA and n-bit rent-Kung, Kogge-Stone, Ladner-Fischer, and Han-Carlson adders. We further show that the Brent-Kung adder has lower delay than the best existing adder designs as well as other prefix adders. In addition, signal integrity and robustness studies show that the proposed Brent-Kung adder is fairly well-suited to changes in time-related parameters as well as temperature. Detailed simulations using QCADesigner are presented. © 2011 IEEE.

Krishnamurthy Sridharan

Department of Electrical Engineering

Area

BRENT-KUNG ADDERS

cell count

KOGGE-STONE ADDER

MAJORITY GATES

QUANTUM DOT CELLULAR AUTOMATA

RIPPLE CARRY ADDERS

Cellular automata

Design

Electric inverters

MAJORITY LOGIC

Semiconductor quantum dots

Sequential machines

Adders

IIT Madras is a public technical and research university located in Chennai, Tamil Nadu. Founded in 1959, it is recognised as an Institute of National Importance.

IIT Madras has been ranked as the top engineering institute in India for four years in a row by the National Institutional Ranking Framework of the MHRD

It currently offers undergraduate, postgraduate and research degrees across 16 disciplines in Engineering, Sciences, Humanities and Management. About 596 faculty belonging to science and engineering departments and centres of the Institute are engaged in teaching, research and industrial consultancy.

IIT Madras

Low Complexity Design of Ripple Carry and Brent–Kung Adders in QCA

IEEE Transactions on Nanotechnology

Several field-effect transistor (FET)-based device technologies are emerging as powerful alternatives to the classical metal oxide semiconductor FET (MOSFET) for computing applications. The focus of this study is on arithmetic circuit design in carbon nanotube FET (CNTFET) technology. In particular, the authors develop low-delay and low-power multi-ternary digit CNTFET-based adder designs. The proposed designs are based on unary operators of multi-valued logic. Efficient designs for primitives such as ternary half-adder (HA) and full-adder are developed and they are used to obtain low-complexity multi-digit adders based on the notions of conditional sum and carry lookahead. Extensive HSPICE simulations reveal that the power-delay product of the proposed CNTFET-based HA and full-adder are roughly 20 and 50%, respectively, of that of recent designs. Further, the proposed CNTFET-based conditional sum adder has a power-delay product of approximately 27% of that of a multi-trit design derived from a recent single-trit adder design (for a load capacitance of 2 fF). Moreover, the proposed CNTFET-based carry lookahead adder has low delay in comparison with the conditional sum strategy for different supply voltages. Studies on robustness of the designs are also reported. © The Institution of Engineering and Technology.

IET Circuits, Devices and Systems

Carbon nanotube FET-based low-delay and low-power multi-digit adder designs

The design of high-performance adders has experienced a renewed interest in the last few years; among high performance schemes, parallel prefix adders constitute an important class. They require a logarithmic number of stages and are typically realized using AND-OR logic; moreover with the emergence of new device technologies based on majority logic, new and improved adder designs are possible. However, the best existing majority gate-based prefix adder incurs a delay of 2log2 (η) 1 (due to the nth carry); this is only marginally better than a design using only AND-OR gates (the latter design has a 2log2 (η) 1 gate delay). This paper initially shows that this delay is caused by the output carry equation in majority gate-based adders that is still largely defined in terms of AND-OR gates. In this paper, two new majority gate-based recursive techniques are proposed. The first technique relies on a novel formulation of the majority gate-based equations in the used group generate and group propagate hardware; this results in a new definition for the output carry, thus reducing the delay. The second contribution of this manuscript utilizes recursive properties of majority gates (through a novel operator) to reduce the circuit complexity of prefix adder designs. Overall, the proposed techniques result in the calculation of the output carry of an n-bit adder with only a majority gate delay of log2 (η) 1. This leads to a reduction of 40percent in delay and 30percent in circuit complexity (in terms of the number of majority gates) for multi-bit addition in comparison to the best existing designs found in the technical literature. © 1968-2012 IEEE.

IEEE Transactions on Computers

Majority logic formulations for parallel adder designs at reduced delay and circuit complexity

In this brief, we consider quantum-dot cellular automata (QCA) realization of the discrete Hadamard transform (DHT). An analysis of a full-parallel solution based on efficient multibit addition in QCA is first presented. We show that this leads to large area as well as delay. We then propose a bit-serial pipelined architecture for QCA-based DHT. The proposed architecture is based on a new one-bit adder-subtractor requiring only six majority gates and a feedback latch that requires only one majority gate and limited wiring. The approach leads to a reduction in area-delay-cycle product of 74% and 91% (over a full-parallel solution) for wordlengths of 4 and 8, respectively. Results of simulations in QCADesigner are also presented. © 2014 IEEE.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

A Bit-Serial Pipelined Architecture for High-Performance DHT Computation in Quantum-Dot Cellular Automata

The design of digital circuits in Quantum Dot Cellular Automata (QCA) has been of active interest in the last decade. While there are many proposals for design of adders, work on subtractors is limited. This paper presents efficient QCA designs of single-bit and multi-bit subtractors. The designs are based on new results on majority logic. Simulations in QCADesigner are presented. The complexity of the proposed designs in terms of cell count and area are also given. © 2013 IEEE.

Proceedings of the IEEE Conference on Nanotechnology

Efficient QCA design of single-bit and multi-bit subtractors

In this study an area optimized Dadda multiplier with a data aware Brent Kung adder in the final addition stage of the Dadda algorithm for improved efficiency has been described in 45 nm technology. Currently the trend is to shift towards low area designs due to the increasing cost of scaled CMOS. An area reduced full adder is the key component in our design. It uses lesser number of gates than conventional design and hence lesser area and delay. The data aware Brent Kung adder in the final addition stage helps in reducing dynamic power as it reduces switching activity depending on the inputs. We have compared the results to the existing benchmark designs and our experimental results show that we have been capable of reducing the area by 13.011% and total power by 26.1% with only a slight increase in the delay. © Maxwell Scientific Organization, 2015.

Fulltext

Research Journal of Applied Sciences, Engineering and Technology

Low Power and Efficient Dadda Multiplier

SDIV of OIP material gets altered with thermal ageing temperature of OIP material, supply voltage frequency and the harmonic content in the supply voltage. The UHF signal radiated due to surface discharges formed under AC voltage, high frequency AC voltages and with harmonic voltages, have dominant frequency at about 0.9 GHz. Surface charge accumulation studies indicate that thermal ageing have high impact on amount of charge accumulation. Also number of layers of insulation have high charge trap density, which is ascertained through tdv/dt plot. The amount of charge accumulated is high with pressboard impregnated in titania nanoparticle dispersed transformer oil. The SD activity occurs at the rising portion of AC voltage and at high dv/dt’s with harmonic AC voltages. More number of discharges occur with OIPs thermally aged at higher temperature. Physico-chemical changes clearly indicate not much of a change occurs with transformer insulation due to thermal ageing. © 2017, School of Electrical Engineering and Informatics. All rights reserved.

International Journal on Electrical Engineering and Informatics

Understanding the surface discharge activity with thermally aged nanofluid impregnated paper insulating material

This paper first presents an efficient quantum-dot cellular automata (QCA) design for the Ladner-Fischer prefix adder. We then present an efficient QCA design of a hybrid adder that combines the Ladner-Fischer adder with a ripple carry adder. We show that the hybrid adder has better performance (in terms of latency) in QCA than a Ladner-Fischer or a ripple carry adder. We also show that the hybrid adder has a smaller area-delay product than existing adder designs in QCA. Results of simulation in QCADesigner are also given and they support the theory presented. © 2010 IEEE.

Efficient design of a hybrid adder in quantum-dot cellular automata

Computer Arithmetic Algorithms

Adder and Multiplier Design in Quantum-Dot Cellular Automata

Analyzing the Inherent Reliability of Moderately Sized Magnetic and Electrostatic QCA Circuits Via Probabilistic Transfer Matrices

Low complexity design of ripple carry and brent-kung adders in QCA

Journal	IEEE Transactions on Nanotechnology
ISSN	1536125X
Open Access	No