This paper presents the implementation of a 3GPP standards compliant configurable turbo decoder on a GPU. The challenge in implementing a turbo decoder on a GPU is in suitably parallelizing the Log-MAP decoding algorithm and doing an architecture aware mapping of it on to the GPU. The approximations in parallelizing the Log-MAP algorithm come at the cost of reduced BER performance. To mitigate this reduction, different guarding mechanisms of varying computational complexity have been presented. The limited shared memory and registers available on GPUs are carefully allocated to obtain a high real-time decoding rate without requiring several independent data streams in parallel. © 2012 IEEE.

Nitin Chandrachoodan

Department of Electrical Engineering

Dhiraj Reddy Nallapa Yoge

3GPP STANDARD

BER PERFORMANCE

CUDA

data stream

DECODING ALGORITHM

DECODING RATES

GPU IMPLEMENTATION

LOG-MAP

LOG-MAP ALGORITHMS

Parallelizing

Shared memories

Software-defined radios

TURBO DECODERS

Approximation algorithms

Decoding

Mobile telecommunication systems

Program processors

Embedded systems

IIT Madras is a public technical and research university located in Chennai, Tamil Nadu. Founded in 1959, it is recognised as an Institute of National Importance.

IIT Madras has been ranked as the top engineering institute in India for four years in a row by the National Institutional Ranking Framework of the MHRD

It currently offers undergraduate, postgraduate and research degrees across 16 disciplines in Engineering, Sciences, Humanities and Management. About 596 faculty belonging to science and engineering departments and centres of the Institute are engaged in teaching, research and industrial consultancy.

IIT Madras

GPU Implementation of a Programmable Turbo Decoder for Software Defined Radio Applications

Proceedings of the IEEE International Conference on VLSI Design

Turbo decoders use the recursive BCJR algorithm which is computationally intensive and hard to parallelise. The branch metric and extrinsic log-likelihood ratio computations are easily parallelisable, but the forward and backward metric computation is not parallelisable without compromising bit error rate. This paper proposes a lossless parallelisation technique for Turbo decoders on Graphics Processing Units (GPU). The recursive forward and backward metric computation is formulated as prefix (scan) matrix multiplication problem which is computed on the GPU using parallel prefix sum computation technique. Overall, this method achieves a throughput of 73 Mbps for a 3GPP LTE compliant turbo decoder without any BER loss and latency as low as 61 μs. © 2018 IEEE.

Proceedings - 25th IEEE International Conference on High Performance Computing, HiPC 2018

Lossless Parallel Implementation of a Turbo Decoder on GPU

Programming Massively Parallel Processors

History of GPU Computing

2010 IEEE Workshop On Signal Processing Systems

Implementation of a 3GPP LTE turbo decoder accelerator on GPU

Proceedings of the 2010 international conference on Compilers, architectures and synthesis for embedded systems - CASES '10

Design space exploration of the turbo decoding algorithm on GPUs

Proceedings of the 36th annual international symposium on Computer architecture - ISCA '09

An analytical model for a GPU architecture with memory-level and thread-level parallelism awareness

IEEE Transactions on Information Theory

Interleavers for turbo codes using permutation polynomials over integer rings

GPU implementation of a programmable turbo decoder for software defined radio applications

Journal	Proceedings of the IEEE International Conference on VLSI Design
ISSN	10639667
Open Access	No