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Field-plate engineering for HFETs
Published in
2005
Volume: 52
   
Issue: 12
Pages: 2534 - 2540
Abstract
This paper reports on the analytical approach for designing field plates for reducing the electric field in the channel and at the surface of heterostructure field-effect transistors (HFETs) for a given drain voltage, with the smallest possible increase of the gate capacitance. The analytical calculations for GaN-based HFETs are in good agreement with the two-dimensional numerical simulations. © 2005 IEEE.
About the journal
JournalIEEE Transactions on Electron Devices
ISSN00189383
Open AccessNo
Concepts (13)
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    Capacitance
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    Computer simulation
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    Electric fields
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    Electric insulators
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    Gallium nitride
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    Gates (transistor)
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    Heterojunctions
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    Mathematical models
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    Analytical modeling
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    FIELD-PLATE ENGINEERING
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    Gate capacitance
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    HETEROSTRUCTURE FIELD-EFFECT TRANSISTORS (HFETS)
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    Field effect transistors