This letter presents an efficient multiternary digit (trit) adder design in carbon nanotube field effect transistor technology. The adder is based on an efficient single-trit full-adder design with low-complexity encoder and reduced complexity carry-generation unit. Further, we optimize the number of encoder and decoder blocks required while putting together several single-trit full-adder units to realize a multitrit adder. Extensive HSPICE simulation results show roughly 79% reduction in power-delay product for three-trit adders and 88 % reduction in power-delay product for nine-trit adders in comparison to a direct realization. © 2002-2012 IEEE.

Krishnamurthy Sridharan

Department of Electrical Engineering

ADDER DESIGN

CARBON NANO-TUBE FIELD EFFECT TRANSISTOR (CNTFET)

CNTFET TECHNOLOGIES

FULL ADDERS

HSPICE SIMULATIONS

POWER-DELAY PRODUCTS

Reduced complexity

TERNARY DIGIT (TRIT)

CARBON NANOTUBE FIELD EFFECT TRANSISTORS

Design

Adders

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IIT Madras

Efficient Multiternary Digit Adder Design in CNTFET Technology

IEEE Transactions on Nanotechnology

Several field-effect transistor (FET)-based device technologies are emerging as powerful alternatives to the classical metal oxide semiconductor FET (MOSFET) for computing applications. The focus of this study is on arithmetic circuit design in carbon nanotube FET (CNTFET) technology. In particular, the authors develop low-delay and low-power multi-ternary digit CNTFET-based adder designs. The proposed designs are based on unary operators of multi-valued logic. Efficient designs for primitives such as ternary half-adder (HA) and full-adder are developed and they are used to obtain low-complexity multi-digit adders based on the notions of conditional sum and carry lookahead. Extensive HSPICE simulations reveal that the power-delay product of the proposed CNTFET-based HA and full-adder are roughly 20 and 50%, respectively, of that of recent designs. Further, the proposed CNTFET-based conditional sum adder has a power-delay product of approximately 27% of that of a multi-trit design derived from a recent single-trit adder design (for a load capacitance of 2 fF). Moreover, the proposed CNTFET-based carry lookahead adder has low delay in comparison with the conditional sum strategy for different supply voltages. Studies on robustness of the designs are also reported. © The Institution of Engineering and Technology.

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Efficient multiternary digit adder design in CNTFET technology

Journal	IEEE Transactions on Nanotechnology
ISSN	1536125X
Open Access	No