This paper presents two area-efficient algorithms and their architectures based on CORDIC. While the first algorithm eliminates ROM and requires only low-complexity barrel shifters, the second eliminates barrel shifters completely. As a consequence, both the algorithms consume approximately 50% area in comparison with other CORDIC designs. Further, the proposed algorithms are applicable to the entire range of angles. The FPGA implementations consume approximately 8% LUTs of a Xilinx Spartan XC2S200E device and have a slice-delay product of about 3. Convergence proofs for the algorithms are presented. Experimental comparisons with prior CORDIC designs confirm the efficacy of the proposed designs. © 2009 IEEE.

Krishnamurthy Sridharan

Department of Electrical Engineering

Algorithms

Digital computers

Field programmable gate arrays (FPGA)

Multicarrier modulation

Rotation

Throughput

AREA-EFFICIENT ALGORITHMS

BARREL SHIFTER

Coordinate Rotation Digital Computer (CORDIC)

CORDIC ALGORITHMS

DELAY PRODUCTS

EXPERIMENTAL COMPARISONS

Extended range

FPGA implementations

LOW AREA AND HIGH THROUGHPUT IMPLEMENTATION

LOW COMPLEXITY

Convergence of numerical methods

IIT Madras is a public technical and research university located in Chennai, Tamil Nadu. Founded in 1959, it is recognised as an Institute of National Importance.

IIT Madras has been ranked as the top engineering institute in India for four years in a row by the National Institutional Ranking Framework of the MHRD

It currently offers undergraduate, postgraduate and research degrees across 16 disciplines in Engineering, Sciences, Humanities and Management. About 596 faculty belonging to science and engineering departments and centres of the Institute are engaged in teaching, research and industrial consultancy.

IIT Madras

Efficient CORDIC Algorithms and Architectures for Low Area and High Throughput Implementation

IEEE Transactions on Circuits and Systems II: Express Briefs

Vector rotation is an important component of algorithms in digital signal processing and robotics. Often, the rotation does not require very high accuracy. This study presents a lowoverhead sign-precomputation-based architecture for approximate rotation using the coordinate rotation digital computer (CORDIC) algorithm. The proposed architecture is independent of Z-datapath, and involves precomputation of the direction of rotation for each micro-rotation angle. The approach involves selecting the optimal micro-rotation angles from a set of elementary angles in run time. Careful selection and elimination of the redundant micro-rotation angles leads to a maximum of three iterations for a majority of the input angles while also simultaneously reaching within 0:45 (of the desired rotation angle). An field programmable gate array (FPGA) implementation of the proposed rotation mode CORDIC on XC7K70T-3FBG676 Kintex-7 using Xilinx ISE 13.2 achieves roughly 50% reduction in slice-delay product and power-delay product compared to recent designs. An application of approximate rotation to Hough transform-based lane detection is presented. An efficient algorithm for generation of vote addresses in the parameter space is proposed. It is shown that accurate lane detection is possible along with resource savings using the proposed CORDIC. The proposed architecture reduces the number of additions roughly by a factor of 20 compared with the conventional method of computing a parameter for each feature point. © The Institution of Engineering and Technology 2018.

IET Circuits, Devices and Systems

Precomputation-based radix-4 CORDIC for approximate rotations and Hough transform

The COordinate Rotation DIgital Computer or CORDIC is an iterative algorithm for computing vector rotation. It uses only shift-and-add operations that make it a popular choice for computing operations such as vector rotation, matrix, trigonometric, hyperbolic, logarithmic and exponential computations in embedded platforms. This paper gives a control perspective to the algorithm by describing it as a switched autonomous nonlinear discrete system. A Lyapunov function-based analysis for switched system is applied to show the stability of the system. This analysis provides a methodology to derive metrics for comparing various variations developed for reducing latency. Further, the switching behavior is analyzed and a novel architecture is developed for reducing latency without any compromise on the metrics. The hardware implementation of novel architecture is based on the attempt to unfold the conventional architecture by predicting the switching signal. © 2019, Springer Science+Business Media, LLC, part of Springer Nature.

Circuits, Systems, and Signal Processing

CORDIC as a Switched Nonlinear System

IEEE Transactions on Computers

A Scale Factor Correction Scheme for the CORDIC Algorithm

IEEE Transactions on Circuits and Systems for Video Technology

Modified virtually scaling-free adaptive CORDIC rotator algorithm and architecture

IEEE Transactions on Circuits and Systems I: Regular Papers

Para-CORDIC: Parallel CORDIC Rotation Algorithm

IEE Proceedings - Computers and Digital Techniques

Virtually scaling-free adaptive CORDIC rotator

Microprocessors and Microsystems

A novel technique for eliminating iterative based computation of polarity of micro-rotations in CORDIC based sine–cosine generators

Efficient CORDIC algorithms and architectures for low area and high throughput implementation

Journal	Data powered by TypesetIEEE Transactions on Circuits and Systems II: Express Briefs
Publisher	Data powered by TypesetInstitute of Electrical and Electronics Engineers Inc.
ISSN	15497747
Open Access	No