Many signal chains need to digitize signals in the presence of interferers. The usual way of accomplishing this is to use an analog anti-alias filter followed by a Nyquist ADC. Continuous-time ΔΣ<math xmlns="http://www.w3.org/1998/Math/MathML"><mi>Δ</mi><mi>Σ</mi></math>&nbsp;modulators (CTΔΣ<math xmlns="http://www.w3.org/1998/Math/MathML"><mi>Δ</mi><mi>Σ</mi></math>&nbsp;M) are compelling alternatives to Nyquist rate ADCs. While oversampling relaxes the requirements of the anti-alias filter, it is natural to wonder if the built-in filtering of a CTΔΣ<math xmlns="http://www.w3.org/1998/Math/MathML"><mi>Δ</mi><mi>Σ</mi></math>&nbsp;M, characterized by its Signal Transfer Function (STF), can be used to attenuate interferers so that an explicit filter up front can be dispensed with altogether. It turns out that the Signal Transfer Function (STF) of a conventional CTΔ ΣM is a by-product of NTF synthesis, with the designer having little control over it. The STF can be independently controlled by using a filter up front—however, this increases power dissipation and degrades linearity of the signal chain. Embedding the filter in the modulator achieves the same objective in a power efficient manner, while improving out-of-band linearity and reducing active area. This work reviews filtering ΔΣ<math xmlns="http://www.w3.org/1998/Math/MathML"><mi>Δ</mi><mi>Σ</mi></math>&nbsp;conversion and circuit techniques for such converters.

Shanthi Pavan Y

Department of Electrical Engineering

Radha Rajan

Electronics engineering

Electronics industry

DELTA-SIGMA CONVERTERS

Design considerations

Power converters

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IIT Madras

Design Considerations for Filtering Delta Sigma Converters

Wideband Continuous-time ΣΔ ADCs, Automotive Electronics, and Power Management: Advances in Analog Circuit Design 2016

Conventional continuous-time delta-sigma modulator (CTDSM) architectures do not allow independent control of the shape and bandwidth of the signal transfer function (STF), since the STF is simply a by-product of NTF synthesis. This is particularly troublesome when the input to the CTDSM consists of large out-of-band interferers; handling them without saturating the quantizer needs larger inband DR, leading to increased power dissipation. A solution to this problem is to use a filter upfront to attenuate interferers. Alternatively [1], the filter can be moved into the CTDSM loop. In [1], a 1st-order RC filter was used to 'tame' the STF peak of a cascade of integrators with feedforward summation (CIFF) DSM. Apart from the limited selectivity offered by a 1st-order filter, an active feedback path was necessary to stabilize the loop. The CTDSM in our work obtains an STF with a sharper transition band and a lower cutoff frequency (normalized to the desired signal bandwidth) compared to [1], with the aim of more effectively attenuating close-in interferers. This is realized by embedding a 2nd-order active filter into the CTDSM. We show that this has the same functionality as the filter upfront, but achieves better linearity (for the same noise and power dissipation) when compared to the filter-CTDSM cascade. Further, no extra active circuitry is necessary to stabilize the loop. Measurements of a CTDSM (signal BW=2MHz), with a built-in VGA (0 to 18dB) and a 2nd-order Butterworth filter (4MHz cutoff), show that the out-of-band IIP3 improves by about 10dB when compared to the CTDSM with the filter placed upfront. The filtering CTDSM+VGA, which uses a single-bit quantizer and a 4-tap FIR DAC, achieves a DR of 92dB in a 2MHz BW while consuming 5mW in a 0.13μm CMOS process. The peak instantaneous DR/SNR/SNDR are 82/80.5/74.5dB. With the VGA, the DR is 92dB. © 2014 IEEE.

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

A 5mW CT ?S ADC with embedded 2nd-order active filter and VGA achieving 82dB DR in 2MHz BW

Continuous-time ΔΣ modulators (CTDSM) used in wireless systems need to process signals in the presence of interferers. Peaking in the Signal Transfer Function of a conventional design necessitates a higher in-band dynamic range to accommodate interferers. A filter up front solves this problem at the expense of increased power dissipation and degraded linearity of the signal chain. Embedding the filter in the modulator achieves the same objective in a power efficient manner, while improving out-of-band linearity and reducing active area. However, having the filter inside a ΔΣ loop can be problematic with respect to stability. We show that such a system can be stabilized in a robust manner without extra hardware. Measurements of a CTDSM (signal BW = 2 MHz), with a built-in VGA (0 to 18 dB) and a second order Butterworth filter (4 MHz cutoff), show that the in-band/out-of-band IIP3 improves by about 3/10 dB when compared to the filter-CTDSM cascade, and achieves a similar dynamic range and consumes 25% lower power. © 1966-2012 IEEE.

IEEE Journal of Solid-State Circuits

Design techniques for continuous-time ΔΣ modulators with embedded active filtering

We present a technique for determining the coefficients of the loop filter in a continuous-time delta sigma modulator (CTDSM) from the corresponding discrete time prototype. The method, which is based on computing the moments of the feedback DAC pulse shape, enables the determination of loop filter coefficients to an arbitrary DAC pulse shape without resorting to z-domain analysis. This not only simplifies the algebra, but also gives new insights into modulator operation. The technique helps derive topologies to compensate CTDSMs with FIR feedback DACs, as well as give closed form expressions for the coefficients of the compensated modulator. Finally, we give simple formulae for coefficients to compensate for excess loop delay in CTDSMs with arbitrary DAC pulses. © 2014 IEEE.

IEEE Transactions on Circuits and Systems I: Regular Papers

Continuous-time delta-sigma modulator design using the method of moments

Conventional continuous-time ΔΣ modulators that use non-return-to-zero (NRZ) feedback DACs suffer from distortion due to intersymbol interference (ISI) and are sensitive to clock jitter. Using a return-to-zero (RZ) DAC solves the problem of ISI, but exacerbates clock jitter sensitivity. The clock jitter sensitivity of an NRZ DAC can be reduced using a switched-capacitor (SC) DAC, but the large peak-to-average ratio of the DAC waveform degrades modulator linearity. In this work, we introduce the switched-capacitor return-to-zero (SCRZ) DAC, which combines the low clock jitter sensitivity of the SC DAC with the low distortion of an RZ DAC. The efficacy of the SCRZ principle is borne out by measurement results from a modulator that achieves a DR/SNR/SNDR of 87.1/84.5/82.3 dB in a 2 MHz bandwidth while dissipating 16.5 mW from a 1.8-V supply. The converter, designed in a 0.18-μ CMOS technology, reduces clock jitter sensitivity by 28 dB when compared with a traditional RZ DAC. © 1966-2012 IEEE.

Continuous-time ΔΣ modulators with improved linearity and reduced clock jitter sensitivity using the switched-capacitor return-to-zero DAC

We give design considerations for single-bit continuous-time Delta-Sigma modulators (CTDSMs) with FIR feedback DACs. These modulators have the low jitter sensitivity and high linearity properties characteristic of a multibit modulator, while using a simple one-bit quantizer, thereby combining the advantages of single-bit and multibit operation. We propose a method to compensate the loop for the delay introduced by the FIR-DAC. The efficacy of our architectural and circuit techniques is borne out by measurement results from a modulator that achieves about 71-dB SNDR in a 36-MHz bandwidth while consuming only 15 mW from a 1.2-V supply. Implemented in a 90-nm CMOS process and sampling at 3.6 GS/s, the CTDSM has a figure of merit (FoM) of 72.7 fJ/lvl, while occupying 0.12 mm2. © 2012 IEEE.

Journal	Data powered by TypesetWideband Continuous-time ΣΔ ADCs, Automotive Electronics, and Power Management: Advances in Analog Circuit Design 2016
Publisher	Data powered by TypesetSpringer International Publishing
Open Access	No