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Data scheduling scheme for power reduction in DWT-based image coders
Kavish Seth
Published in
Volume: 38
Issue: 9
Pages: 408 - 409
A new memory data scheduling scheme is used for designing a two-dimensional discrete wavelet transform (2D-DWT) core for ASIC implementation. This scheme reduces by 20 to 30% the overall switching activity in the 2D-DWT core and hence leads to lower power consumption at the expense of a slight reduction in the quality of reconstructed images and a slight increase in the chip area. This scheme is particularly useful in applications such as wireless Internet and laptop computers, in which picture quality can be traded-off for reduced power consumption.
About the journal
JournalElectronics Letters
Open AccessNo
Concepts (11)
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    Cosine transforms
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    Discrete fourier transforms
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    Image compression
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    Image quality
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    Shift registers
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    Wavelet transforms
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    Data scheduling
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    Discrete wavelet transforms
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    Image coding