A new memory data scheduling scheme is used for designing a two-dimensional discrete wavelet transform (2D-DWT) core for ASIC implementation. This scheme reduces by 20 to 30% the overall switching activity in the 2D-DWT core and hence leads to lower power consumption at the expense of a slight reduction in the quality of reconstructed images and a slight increase in the chip area. This scheme is particularly useful in applications such as wireless Internet and laptop computers, in which picture quality can be traded-off for reduced power consumption.

Kavish Seth

Cosine transforms

Discrete Fourier transforms

Image compression

Image quality

OPTICAL FILTERS

scheduling

Shift registers

Wavelet transforms

Data scheduling

Discrete wavelet transforms

Image coding

IIT Madras is a public technical and research university located in Chennai, Tamil Nadu. Founded in 1959, it is recognised as an Institute of National Importance.

IIT Madras has been ranked as the top engineering institute in India for four years in a row by the National Institutional Ranking Framework of the MHRD

It currently offers undergraduate, postgraduate and research degrees across 16 disciplines in Engineering, Sciences, Humanities and Management. About 596 faculty belonging to science and engineering departments and centres of the Institute are engaged in teaching, research and industrial consultancy.

IIT Madras

Electronics Letters

This paper presents architectures and scheduling algorithms for the 2-D Discrete Wavelet Transform (DWT) and the Inverse Discrete Wavelet Transform (IDWT) using 9/7-tap filter banks based on the Non-expansive Symmetric Extension (NSE) scheme that reduces distortion at boundaries of the reconstructed image. The hardware has been implemented for image blocks of size 32 x 32 pixels, up to third level of transform, and cuts down the power consumption at the architecture level by incorporating three techniques, viz., Canonic Sign Digit (CSD) and common subexpression sharing technique, Gray code addressing mode and resource sharing. The implementation has been tested using 0.35 μm (three metal) technology by simulation at functional, circuit and physical levels. The performance measures of implementation, viz., area, memory requirement, speed and power have been evaluated. © 2002 IEEE.

Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002

VLSI implementation of 2-D DWT/IDWT cores using 9/7-tap filter banks based on the non-expansive symmetric extension scheme

Applied and Computational Harmonic Analysis

Classification of Nonexpansive Symmetric Extension Transforms for Multirate Filter Banks

IEEE Transactions on Circuits and Systems for Video Technology

A new, fast, and efficient image codec based on set partitioning in hierarchical trees

IEEE Transactions on Acoustics, Speech, and Signal Processing

Analysis/synthesis techniques for subband image coding

Data scheduling scheme for power reduction in DWT-based image coders

Journal	Electronics Letters
ISSN	00135194
Open Access	No