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CHOAMP: Cost Based Hardware Optimization for Asymmetric Multicore Processors
Published in Institute of Electrical and Electronics Engineers Inc.
2018
Volume: 4
   
Issue: 2
Pages: 163 - 176
Abstract
Heterogeneous Multiprocessors (HMPs) are popular due to their energy efficiency over Symmetric Multicore Processors (SMPs). Asymmetric Multicore Processors (AMPs) are a special case of HMPs where different kinds of cores share the same instruction set, but offer different power-performance trade-offs. Due to the computational-power difference between these cores, finding an optimal hardware configuration for executing a given parallel program is quite challenging. An inherent difficulty in this problem stems from the fact that the original program is written for SMPs. This challenge is exacerbated by the interplay of several configuration parameters that are allowed to be changed in AMPs. In this work, we propose a probabilistic method named to choose the best available hardware configuration for a given parallel program. Selection of a configuration is guided by a user-provided run-time property such as energy-delay-product (EDP) and aspires to optimize the property in choosing a configuration. The core part of our probabilistic method relies on identifying the behavior of various program constructs in different classes of CPU cores in the AMP, and how it influences the cost function of choice. We implement the proposed technique in a compiler which automatically transforms a code optimized for SMP to run efficiently over an AMP, eliding requirement of any user annotations. Transforms the same source program for different hardware configurations based on different user requirement. We evaluate the efficiency of our method for three different run-time properties: execution time, energy consumption, and EDP, in NAS Parallel Benchmarks for OpenMP. Our experimental evaluation shows that achieves an average of 65, 28, and 57 percent improvement over baseline HMP scheduling while optimizing for energy, execution time, and EDP, respectively. © 2015 IEEE.
About the journal
JournalData powered by TypesetIEEE Transactions on Multi-Scale Computing Systems
PublisherData powered by TypesetInstitute of Electrical and Electronics Engineers Inc.
ISSN23327766
Open AccessNo
Concepts (20)
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    Application programming interfaces (api)
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    Computer hardware
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    Cost functions
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    Economic and social effects
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    Energy efficiency
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    Energy utilization
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    Hardware
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    Parallel processing systems
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    Program compilers
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    Scheduling
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    Shape memory effect
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    ASYMMETRIC MULTICORE
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    BIG.LITTLE
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    Compiler optimizations
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    HARDWARE CONFIGURATIONS
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    Instruction set
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    MULTI-CORE PROCESSING
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    Power demands
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    Processor scheduling
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    MULTICORE PROGRAMMING