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Architecturally-efficient computation of shortest paths for a mobile robot
Krishnamurthy Sridharan
Published in
2009
DOI:
10.1109/ISIEA.2009.5356447
Volume: 1
Pages: 277 - 282
Abstract
The computation of shortest path for a mobile robot to get to a destination is considered in this paper. An architecturally-efficient solution is presented for this problem. Results of implementation in Xilinx Virtex FPGA are promising: the solution operates at approximately 72 MHz and the implementation for a graph with 40 nodes and 52 edges fits in one XCV3200E-FG1156 device. © 2009 IEEE.
Topics:
K shortest path routing
(62)%
62% related to the paper
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Shortest path problem
(60)%
60% related to the paper
,
Mobile robot
(58)%
58% related to the paper
and
Virtex
(56)%
56% related to the paper
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Journal
2009 IEEE Symposium on Industrial Electronics and Applications, ISIEA 2009 - Proceedings
Open Access
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Authors (1)
Krishnamurthy Sridharan
Department of Electrical Engineering
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Concepts (7)
Efficient computation
Shortest path
Field programmable gate arrays (fpga)
Graph theory
Industrial electronics
Wireless sensor networks
Mobile robots
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