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Analysis and design of a 20-MHz bandwidth continuous-time delta-sigma modulator with time-interleaved virtual-ground-switched FIR feedback
, Baluni A.
Published in Institute of Electrical and Electronics Engineers Inc.
Volume: 56
Issue: 3
Pages: 729 - 738
We present the design principles and circuit details of a single-bit continuous-time delta-sigma ADC that achieves 13.3-bit resolution over a 20-MHz signal bandwidth. The modulator, which operates at a sampling rate of 2.56 GHz in a 65-nm CMOS process, uses a 2 × time-interleaved ADC to address the problem of comparator metastability. A 4 × time-interleaved virtual-ground-switched resistive FIR feedback DAC is used for low distortion and power-efficient operation. Interleaving artifacts caused by DAC-element mismatch are addressed by mixed-signal calibration, which is enabled by the DAC architecture. The decimator is implemented using poly-phase techniques. A prototype modulator, which operates with a 1.1-V supply, achieves 82.1-dB peak SNDR and THD of 98.6 dBc while consuming 11.3 mW. The resulting Schreier FoM is 174.1 dB. The decimator dissipates 13.5 mW. © 1966-2012 IEEE.
About the journal
JournalData powered by TypesetIEEE Journal of Solid-State Circuits
PublisherData powered by TypesetInstitute of Electrical and Electronics Engineers Inc.
Open AccessNo