An accurate analytic model is proposed for estimating the junction temperature and thermal resistance in silicon-germanium heterojunction bipolar transistors (SiGe HBTs) including the back-end-of-line (BEOL) metal layers. The model uses an average value of thermal conductivity in order to include the temperature dependence of thermal resistance. The parameters corresponding to the thermal conductivity and the BEOL thermal resistance used in the model are extracted following a recently reported methodology. The proposed model is scalable in nature and verification with experimental data shows an excellent accuracy across different emitter geometries of SiGe HBTs fabricated in STMicroelectronics B9MW technology. Compact model simulations show that the proposed model simulates around 23% faster compared with an existing state-of-the-art iterative method. © 1963-2012 IEEE.

Anjan Chakravorty

Department of Electrical Engineering

Analytical models

Germanium

Heat resistance

Heterojunctions

Iterative methods

Si-Ge alloys

Silicon alloys

Silicon wafers

Temperature distribution

Thermal conductivity

Tungsten alloys

Analytic modeling

Back end of lines

ITERATIVE MODEL

self-heating

SiGe HBTs

Heterojunction bipolar transistors

IIT Madras is a public technical and research university located in Chennai, Tamil Nadu. Founded in 1959, it is recognised as an Institute of National Importance.

IIT Madras has been ranked as the top engineering institute in India for four years in a row by the National Institutional Ranking Framework of the MHRD

It currently offers undergraduate, postgraduate and research degrees across 16 disciplines in Engineering, Sciences, Humanities and Management. About 596 faculty belonging to science and engineering departments and centres of the Institute are engaged in teaching, research and industrial consultancy.

IIT Madras

Accurate Modeling of Thermal Resistance for On-Wafer SiGe HBTs Using Average Thermal Conductivity

IEEE Transactions on Electron Devices

In this brief, we propose a simple approach to extract the contribution of the back-end-of-line (BEOL) layers on the thermal resistance of heterojunction bipolar transistors (HBTs). A finite value of BEOL thermal resistance obtained following our approach confirms a non-negligible heat flow toward BEOL. The proposed extraction technique is validated with iterative solutions and measured data of silicon-germanium HBTs fabricated in the STMicroelectronics B9MW technology. © 1963-2012 IEEE.

Extraction of BEOL Contributions for Thermal Resistance in SiGe HBTs

In this paper we present an improved self-consistent iterative model for thermal resistance in SiGe HBTs. The proposed model evaluates both the upward and downward heat dissipation from the heat source located at the base-collector junction. Along with the temperature dependency, thermal conductivity degradation due to heavy doping and Ge composition in the base region is included in the proposed model. It is observed that the model accuracy is improved once these physical effects are included along with the upward heat diffusion. Scalability of the proposed model is validated with the measured data for different emitter geometries. © 2016 IEEE.

Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting

An improved scalable self-consistent iterative model for thermal resistance in SiGe HBTs

In this paper, we propose a new method for estimating the peak junction temperature and thermal resistance in modern heterojunction bipolar transistors (HBTs). The proposed method uses the temperature dependence of thermal conductivity of the material. The method is analytic in nature and does not require any iteration as opposed to the existing state-of-the-art model. This analytic method can easily include the available scaling relations relevant to specific technology to estimate the junction temperatures and thermal resistances of the corresponding transistors. The analytic model is tested against iterative self-consistent solutions for simple structures without any trench isolation and for structures corresponding to the ST Microelectronics B9MW technology that includes shallow and deep trench isolations. The model is slightly modified in order to include the effects from the back-end-of-line metal layers. The resulting analytic model is validated against the measured results for silicon germanium HBTs fabricated in ST Microelectronics B9MW technology. © 1963-2012 IEEE.

Analytic Estimation of Thermal Resistance in HBTs

This paper investigates alternative topologies of silicon germanium heterojunction bipolar transistors designed and fabricated in the state-of-the-art BiCMOS process from STMicroelectronics for improved safe-operating characteristics. Electrical and thermal behaviors of various structures are analyzed and compared, along with a detailed discussion on drawbacks and advantages. The test structures under study are different in terms of emitter-finger layouts as well as the metal stacks in the back-end-of-line. It is observed that the multifinger transistor structures having nonuniform finger lengths with wider area enclosed by the deep trench and higher metallization stacks yield an improved thermal behavior. Therefore, the safe-operating area of multifinger transistors can be extended without degrading the RF performances. © 2016 IEEE.

Innovative SiGe HBT Topologies with Improved Electrothermal Behavior

Microelectronics Reliability

Advanced thermal simulation of SiGe:C HBTs including back-end-of-line

Journal	Data powered by TypesetIEEE Transactions on Electron Devices
Publisher	Data powered by TypesetInstitute of Electrical and Electronics Engineers Inc.
ISSN	00189383
Open Access	No