This brief presents a resource-efficient VLSI architecture for convolution operations in deep networks. Taking advantage of a feature of the max pooling layer in classical convolutional neural networks (CNNs), the image pixels are scaled such that the weight values are constrained to lie in [-1, +1] range. Under this constraint, the weight parameters are chosen as trigonometric functions, enabling realization of convolution without multipliers. In particular, the convolution is realized using the CORDIC algorithm. We also propose a dataflow model based on a reconfigurable systolic ring array to achieve performance comparable to contemporary CNN architectures but with substantially less hardware, high resource utilization efficiency, and reduced power consumption. FPGA implementation of the proposed architecture on Xilinx Virtex-5 XC5VLX5OT achieves roughly 55% higher resource efficiency, with approximately 53% reduction in the slice-delay product and 55% reduction in power consumption compared to recent architectures. © 2004-2012 IEEE.