Analytical placement engines use half-perimeter wire length (HPWL) of the circuit as an objective function to place blocks optimally within a chip. Inspired by popularly used log sum-exp (LSE) wire length model [6], ABS wire length model [5] and weighted average (WA) wire length model [3], we propose a new recursive wire length model for HPWL, providing smooth approximation to the max function. We show that the accuracy of the new model is better than that of LSE, WA and ABS wire length models, both theoretically and experimentally. When deployed inside an analytical engine, we show that our model provides more than 12% reduction in wire length compared to LSE at the expense of 50% more runtime. We also observed that the proposed model and the existing iterative models differ in their impact on the relative effort that has to be put in at the global placement vs. The detailed placement phase. © 2015 IEEE.