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A hardware accelerator and FPGA realization for reduced visibility graph construction using efficient bit representationsPublished in
2007
Volume: 54
Issue: 3
Pages: 1800 - 1804
The reduced visibility graph (RVG) is an important structure for computation of shortest paths for mobile robots. An efficient bit representation is proposed to construct segments that are part of the RVG. Based on the bit representation, a hardware-efficient scheme is presented whose computational complexity is O(k2 log(n/k)), where k is the number of objects and n is the total number of vertices. An architecture that accomplishes the construction of the RVG without division or explicit intersection point calculations is proposed. An efficient field-programmable gate array implementation using block random access memory on an XCV3200E device is presented. © 2007 IEEE.
Topics: Visibility graph (58)%58% related to the paper, Computational complexity theory (51)%51% related to the paper, Representation (mathematics) (50)%50% related to the paper and Hardware acceleration (50)%50% related to the paper
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Related Papers (3)
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Open Access
About the journal
| Journal | IEEE Transactions on Industrial Electronics |
|---|---|
| ISSN | 02780046 |
| Open Access | No |
Authors (1)
Krishnamurthy Sridharan- A parallel algorithm, architecture and FPGA realization for high speed determination of the complete visibility graph for convex objects
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Concepts (15)
FIELD-PROGRAMMABLE GATE ARRAY IMPLEMENTATIONS- HARDWARE ACCELERATORS
- INTERSECTION POINTS
- RANDOM ACCESS MEMORIES
- REDUCED VISIBILITY
- REDUCED VISIBILITY GRAPH (RVG)
- Shortest path
- Computational complexity
- Logic gates
- Random access storage
- Robotics
- Robots
- Unmanned aerial vehicles (uav)
- Visibility
- Field programmable gate arrays (fpga)
