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140 Publications
86 Journals
Veezhinathan Kamakoti
Director
Department of Computer Science and Engineering
kama@iitm.ac.in (Work)
+91-4422574368 (Work)
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Publications - 140
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Publications (140)
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Publications (140)
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Conferences
Controllability-driven power virus generation for digital circuits
K. Najeeb
and
Veezhinathan Kamakoti
2007
Conferences
Glitch-aware pattern generation and optimization framework for power-safe scan test
Veezhinathan Kamakoti
2007
Conferences
A genetic approach to gateless custom VLSI design flow
Veezhinathan Kamakoti
2007
Conferences
A stochastic pattern generation and optimization framework for variation-tolerant, power-safe scan test
Veezhinathan Kamakoti
2007 | Institute of Electrical and Electronics Engineers Inc.
Conferences
LFSR based stream ciphers are vulnerable to power attacks
Sanjay Burman
and
Veezhinathan Kamakoti
2007
Articles
A novel approach to the placement and routing problems for field programmable gate arrays
Veezhinathan Kamakoti
2007
Conferences
On power-profiling and pattern generation for power-safe scan tests
Veezhinathan Kamakoti
2007
Conferences
Power virus generation using behavioral models of circuits
K. Najeeb
and
Veezhinathan Kamakoti
2007
Conferences
PMScan: A power-managed scan for simultaneous reduction of dynamic and leakage power during scan test
Veezhinathan Kamakoti
2007 | Institute of Electrical and Electronics Engineers Inc.
Articles
Variation-tolerant, power-safe pattern generation
Veezhinathan Kamakoti
2007
Conferences
Reducing SoC test time and test power in hierarchical scan test: Scan architecture and algorithms
Veezhinathan Kamakoti
2007
Conferences
Ultra folded high-speed architectures for reed-solomon decoders
Kavish Seth
and
Veezhinathan Kamakoti
2006
Conferences
Delay and peak power minimization for on-chip buses using temporal redundancy
K. Najeeb
,
Mutyam Madhu
and
Veezhinathan Kamakoti
2006
Conferences
An area and configuration-bit optimized CLB architecture and timing-driven packing for FPGAs
Vivek Garg
,
M. Sashikanth
and
Veezhinathan Kamakoti
2006
Conferences
Efficient building blocks for reversible sequential circuit design
Veezhinathan Kamakoti
2006
Articles
A novel CLB architecture and circuit packing algorithm for logic-area reduction in SRAM-based FPGAs
Garg Vivek
,
Chandrasekhar Vikram
,
...
,
Veezhinathan Kamakoti
(4 authors)
2005 | ACM Press
Conferences
A function generator-based reconfigurable system
Vivek Garg
,
M. Sashikanth
and
Veezhinathan Kamakoti
2005
Conferences
Cluster-based detection of SEU-caused errors in LUTs of SRAM-based FPGAs
M. Sashikanth
and
Veezhinathan Kamakoti
2005
Conferences
Detecting SEU-caused routing errors in SRAM-based FPGAs
E. Syam Sundar Reddy
,
M. Sashikanth
and
Veezhinathan Kamakoti
2005
Conferences
A framework for automatic assembly program generaor (A2PG) for verification and testing of processor cores
K. Uday Bhaskar
and
Veezhinathan Kamakoti
2005
Showing 81-100 of 140 results
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