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140 Publications
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Veezhinathan Kamakoti
Director
Department of Computer Science and Engineering
kama@iitm.ac.in (Work)
+91-4422574368 (Work)
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Publications - 140
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Publications (140)
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Publications (140)
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Reviews
Motion vector recovery based error concealment for H.264 video communication: A review
Kavish Seth
and
Veezhinathan Kamakoti
2011
Articles
Thread synchronization: From mutual exclusion to transactional memory
Veezhinathan Kamakoti
2011
Conferences
Towards quick solutions for generalized placement problem
Veezhinathan Kamakoti
2011
Conferences
A simulation based buffer sizing algorithm for network on chips
Veezhinathan Kamakoti
2011
Conferences
Impact of temperature on test quality
Lavanya Jagan
and
Veezhinathan Kamakoti
2010
Conferences
Fast motion vector recovery algorithm in H.264 video streams
Kavish Seth
and
Veezhinathan Kamakoti
2010
Conferences
Constructing online testable circuits using reversible logic
Veezhinathan Kamakoti
2010
Articles
Test and diagnostic trends for nanometer technology
Lavanya Jagan
and
Veezhinathan Kamakoti
2010
Articles
Efficient motion vector recovery algorithm for H.264 using directional interpolation
Kavish Seth
and
Veezhinathan Kamakoti
2010
Articles
Efficient motion vector recovery algorithm for H.264 using B-spline approximation
Kavish Seth
and
Veezhinathan Kamakoti
2010
Conferences
A low-bit rate segment vocoder using minimum residual energy criteria
Hema Murthy
,
Abhijit Pradhan
,
...
,
Veezhinathan Kamakoti
(4 authors)
2010 | IEEE
Conferences
HTM design spaces: Complete decoupling from caches and achieving highly concurrent transactions
Veezhinathan Kamakoti
2009
Conferences
Efficient grouping of fail chips for volume Yield diagnostics
Lavanya Jagan
and
Veezhinathan Kamakoti
2009
Other
Studies on the performance of two new bus arbitration schemes for multi-core processors
Veezhinathan Kamakoti
,
M. Balasubramanian
and
P. Krishnankutty
2009 | IEEE
Articles
Novel SAT-based peak dynamic power estimation for digital circuits
Veezhinathan Kamakoti
2009
Conferences
Test power reduction using integrated scan cell and test vector reordering techniques on linear scan and double tree scan architectures
Veezhinathan Kamakoti
2009
Articles
A novel power-managed scan architecture for test power and test time reduction
Veezhinathan Kamakoti
2008
Articles
Automatic constraint based test generation for behavioral HDL models
Veezhinathan Kamakoti
2008
Articles
System-on-programmable-chip implementation for on-line face recognition
A. Pavan Kumar
,
Sukhendu Das
and
Veezhinathan Kamakoti
2007
Articles
An efficient digital architecture for principal component neural network and its fpga implementation
C. H.Siva Sai Prasanna
and
Veezhinathan Kamakoti
2007
Showing 61-80 of 140 results
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