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It currently offers undergraduate, postgraduate and research degrees across 16 disciplines in Engineering, Sciences, Humanities and Management. About 596 faculty belonging to science and engineering departments and centres of the Institute are engaged in teaching, research and industrial consultancy.

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On-chip buses in deep-submicron designs have large propagation delay due to dominant coupling capacitance. As delay impacts system performance, several techniques have been proposed in the literature to minimize it. A common point in most of the existing techniques is to consider uniformly distributed random data, but propagation delay is data dependent and data is application dependent. Different applications may have different data behaviors. The existing techniques which consider uniformly distributed random data may not exploit the exact data behavior of an application and hence can give inferior performance results. By exploiting similarity in the data transmitted on on-chip buses, we propose three delay minimization techniques, namely, data packing (DPack), data permutation (DPerm), and data replication with shielding and two-phase transmission (RESTP). We show that for a 5-mm 32-bit on-chip bus in 90 nm CMOS technology, the DPack, DPerm, and RESTP techniques achieve more than 25%, 32%, and 51% delay savings, respectively, in both address and data buses. For a 32-bit bus, the DPack, DPerm, and RESTP techniques require 38, 34, and 48 wires, respectively. © 2009 Elsevier B.V. All rights reserved.

Department of Computer Science and Engineering

Microprocessors and Microsystems

Delay-efficient bus encoding techniques

Fabricating circuits that employ ever-smaller transistors leads to dramatic variations in critical process parameters. This in turn results in large variations in execution/access latencies of different hardware components. This situation is even more severe for memory components due to minimum-sized transistors used in their design. Current design methodologies that are tuned for the worst case scenarios are becoming increasingly pessimistic from the performance angle, and thus, may not be a viable option at all for future designs. This paper makes two contributions targeting on-chip data caches. First, it presents an adaptive cache management policy based on nonuniform cache access. Second, it proposes a latency compensation approach that employs several circuit-level techniques to change the access latency of select cache lines based on the criticalities of the load instructions that access them. Our experiments reveal that both these techniques can recover significant amount of the lost performance due to worst case designs. © 2009 IEEE.

IEEE Transactions on Computers

Process variation-aware adaptive cache architecture and management

As on-chip interconnect in deep-submicron designs contribute to the system-wide power consumption, minimization of interconnect power consumption has become one of the important design issues in deep-submicron technologies. As transition activity mainly determines the interconnect power consumption, several bus encoding techniques have been proposed to minimize the activity. Unlike the existing low-power or energy-efficient bus encoding techniques, in this paper, we propose a scheme which exploits both dynamic voltage scaling and variable cycle transmission mechanisms for minimizing on-chip interconnect energy consumption. We transmit data using variable cycle transmission method and, based on the delay savings achieved through variable cycle transmission method at regular intervals, scale the voltage and frequency to obtain significant energy savings. Using our technique for a 5mm interconnect wire we achieved energy savings of 30% and 45% over the base case in the address bus and data bus, respectively. Our technique also reduces the energy-delay-product by 34% and 52% for address bus and data bus, respectively. © 2008 IEEE.

Proceedings of the IEEE International Frequency Control Symposium and Exposition

Exploiting variable cycle transmission for energy-efficient on-chip interconnect design

With reducing feature size, the effects of process variations are becoming more and more predominant. Memory components such as on-chip caches are more susceptible to such variations because of high density and small sized transistors present in them. Process variations can result in high access latency and leakage energy dissipation. This may lead to a functionally correct chip being rejected, resulting in reduced chip yield. In this paper, by considering a process variation affected on-chip data cache, we first analyze performance loss due to worst-case design techniques such as accessing the entire cache with the worst-case access latency or turning off the process variation affected cache blocks, and show that the worst-case design techniques result in significant performance loss and/or high leakage energy. Then by exploiting the fact that not all applications require full associativity at set-level, we propose a variation-tolerant design technique, namely, block remap with turnoff (BRT), to minimize performance loss and leakage energy consumption. In BRT technique we selectively turnoff few blocks after rearranging them in such a way that all sets get almost equal number of process variation affected blocks. By turning off process variation affected blocks of a set, leakage energy can be minimized and the set can be accessed with low latency at the cost of reduced set associativity. We validate our technique by running SPEC2000 CPU benchmark-suite on Simplescalar simulator and show that our technique significantly reduces the performance loss and leakage energy consumption due to process variations. ©2008 IEEE.

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Block remap with turnoff: A variation-tolerant cache design technique

Faced with the challenge of finding ways to use an evergrowing transistor budget, microarchitects have begun to move towards the chip multiprocessors (CMPs) as an attractive solution. CMPs have become a common way of reducing chip complexity and power consumption while maintaining high performance. Multiple cores are replicated on a single chip, resulting in a potential linear scaling of performance. Cores are becoming sufficiently small with technology scaling. As technology continues to scale, inter-die and intra-die variations in process parameters can result in significant impact on performance and power consumption, leading to asymmetry among the cores that were designed to be symmetric. Adaptive voltage scaling can be used to bring all cores to the same performance level leaving only core-to-core power variations. The goal of our work is to find the optimal frequency that balances performance with power against asymmetry. We also demonstrate that traditional task scheduling techniques need to be revisited to mitigate the effects of process variations. Copyright 2008 ACM.

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Power management of variation aware chip multiprocessors

In sub-90nm process technology it becomes harder to control the fabrication process, which in turn causes variations between the design-time parameters and the fabricated parameters. Variations in the critical process parameters can result in significant fluctuations in the switching speed and leakage power consumption of different transistors in the same chip. In this paper, we study the impact of process variation on issue queues. Due to process variation, issue queues can take variable access latency. In order to work with non-uniform access latency issue queues, by exploiting ready operands of instructions at dispatch time, we propose a process variation aware issue queue design. Experimental results reveal that, for a 64-entry issue queue with half of the entries affected by process variation, our technique recovers most of the lost performance due to process variation and incurs a performance penalty of less than 2% with respect to the performance of issue queues without process variation. © 2008 EDAA.

GENERAL

Proceedings -Design, Automation and Test in Europe, DATE

Process variation aware issue queue design

We propose a novel energy-efficient data cache architecture, namely, word-interleaved (WI) cache. In the WI cache, a cache block is distributed uniformly among the different cache ways and each line of a cache way holds some words of the block. This distribution provides an opportunity to activate/deactivate the cache ways based on the requested address's offset, thus minimizing the overall cache access energy. For a 4-way set associative cache of size 16KB and blocksize 3213, the proposed technique accomplishes dynamic energy savings of 54.2% without considering fast hits and 62.3% when fast hits are considered, with small performance degradation and negligible area overhead. Copyright 2008 ACM.

Proceedings of the International Symposium on Low Power Electronics and Design

Word-interleaved cache: An energy efficient data cache architecture

With CMOS process technology scaling to deep submicron level, propagation delay across long on-chip buses is becoming one of the main performance limiting factors in high-performance designs. Propagation delay is very significant when adjacent wires are transitioning in opposite direction (i.e., crosstalk transitions) as compared to transitioning in the same direction. As crosstalk transitions have significant impact on propagation delay, several bus encoding techniques have been proposed in literature to eliminate such transitions. In this work, we propose a technique, namely, selective shielding, to eliminate crosstalk transitions. Compared to the conventional shielding technique, our technique significantly reduces the number of extra wires. We give a lower bound on the number of wires required to encode n-bit data using the selective shielding technique. We show that our technique achieves better energy savings and requires less area as compared to the other techniques. ©2007 IEEE.

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Selective shielding: A crosstalk-free bus encoding technique

On-chip buses in deep-submicron designs have large propagation delay due to dominant coupling capacitance. As delay impacts system performance, several techniques have been proposed in literature to minimize it. A common point in most of the existing techniques is to consider uniformly distributed random data, but the propagation delay is data dependent and data is application dependent. Different applications may have different data behavior. The existing techniques which consider uniformly distributed random data may not exploit the exact data behavior of an application and hence can give different performance results. In this paper, by exploiting data behavior, we propose two on-chip delay minimization techniques, namely, data packing and data permutation. We validate our techniques by focusing on the L1 cache address/data buses using SPEC2000 CINT benchmarks. We show that, in the address bus case, the data packing and data permutation techniques achieve more than 2.3X and 1.6X speedup, respectively, over the unencoded bus, whereas in the case of data bus, both these techniques achieve more than 1.5X and 1.4X speedup, respectively. For a 32-bit bus, both data packing and data permutation techniques require 38 and 34 wires, respectively. Copyright 2007 ACM.

Department Of Civil Engineering

World University root node

International Workshop on System Level Interconnect Prediction, SLIP

Exploiting on-chip data behavior for delay minimization

Process related variations are considered a major concern in emerging sub-65nm technologies. In this paper, we investigate the impact of process variations on different types of content addressable memories (CAM). As CAM structures are used in various on-chip structures such as caches and TLBs, understanding process variation impact of CAM structures is important. To gain insight on the relative importance of process variation effects, we also examine the effect of variability due to temperature and supply voltage changes. Our results show that the NAND-type CAM cells are more susceptible to failures as compared to NOR-type CAM cells. Finally, we propose an architectural technique to mitigate the performance degradation effects of process variation. The proposed technique yields an average of 37.5% 25% and 12.5% reduction in CAM occupancy for caches with 25% 50% and 75% variation respectively, over SPEC 2000 CPU benchmarks as compared to a worst-case design in the presence of process variation. © 2007 IEEE.

Proceedings - Eighth International Symposium on Quality Electronic Design, ISQED 2007

Variation analysis of CAM cells

Deep-submicron designs have to take care of process variation effects as variations in critical process parameters result in large variations in access latencies of hardware components. This is severe in the case of memory components as minimum sized transistors are used in their design. In this work, by considering on-chip data caches, we study the effect of access latency variations on performance. We discuss performance losses due to the worst-case design, wherein the entire cache operates with the worst-case process variation delay, followed by process variation aware cache designs which work at set-level granularity. We then propose a technique called block rearrangement to minimize performance loss incurred by a process variation aware cache which works at set-level granularity. Using block rearrangement technique, we rearrange the physical locations of cache blocks such that a cache set can have its "n" blocks (assuming a n-way set-associative cache) in multiple rows instead of a single row as in the case of a cache with conventional addressing scheme. By distributing blocks of a cache set over multiple sets, we minimize the number of sets being affected by process variation. We evaluate our technique using SPEC2000 CPU benchmarks and show that our technique achieves significant performance benefits over caches with conventional addressing scheme. © 2007 EDAA.

Working with process variation aware caches

Multiport register files are a key component in the design and operation of high performance microprocessors. Due to the frequency of accesses of these register files per clock cycle errors manifested here can potentially spread rapidly. This can seriously compromise the validity of data and even system reliability. Errors may be caused from any number of possible sources including radiation induced soft errors, read or write errors, and permanent device errors. This work focuses on combating errors that affect a stored entry in a register file, but our techniques can often also detect and recover from many other potential sources of errors. Up to 4 bit errors are detectable with 6.25% storage overhead over an unprotected register file. The recovery for most types of errors requires in the order of a few nanoseconds and requires 4% less energy than a monolithic register file with comparable characteristics but no error protection. © 2007 IEEE.

Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures

Investigating simple low latency reliable multiported register files

In this paper, we propose a novel temporal redundancy based encoding technique for delay and peak power minimization. The proposed encoding scheme is tested with the SPEC2000 CINT benchmarks for 90nm and 65nm technologies. The experimental results show that our approach is very effective in reducing the peak power. From the delay perspective, our approach reduces the delay by at least 11% (4%) in the address (data) buses compared to the data transmission without encoding. Copyright 2006 ACM.

Delay and peak power minimization for on-chip buses using temporal redundancy

As processors, memories, and other components of today's embedded systems are pushed to higher performance in more enclosed spaces, processor thermal management is quickly becoming a limiting design factor. While previous proposals mostly approached this thermal management problem from circuit and architecture angles, software can also play an important role in identifying and eliminating thermal hotspots as it is the main factor that shapes the order and frequency of accesses to different hardware components in the chip. This is particularly true for compiler-scheduled Very Long Instruction Word (VLIW) datapath.In this paper, we focus on a compiler-based approach to make the thermal profile more balanced in the integer functional units of VLIW architectures. For balanced thermal behavior and peak temperature minimization, we propose techniques based on load balancing across the integer functional units with or without rotation of functional unit usage. As leakage power is exponentially dependent on temperature and temperature is dependent on total power (i.e., switching and leakage), in our techniques, we also consider leakage power optimization by IPC tuning (instructions issued per cycle). By taking a code that is already scheduled for maximum performance as input, our scheduling strategies modify this performance-oriented schedule for balanced thermal behavior with negligible performance degradation. We simulate our scheduling strategies using a framework that consists of the Trimaran infrastructure, a power model, and the HotSpot. Our experimental results using several benchmark programs reveal that the peak temperature can be reduced through compiler scheduling.

ACM SIGPLAN Notices

Compiler-directed thermal management for VLIW functional units

On-chip buses in deep sub-micron designs consume significant amounts of power and have large propagation delays. Thus, minimizing power consumption and propagation delay are the most important design objectives. In this paper, we propose a technique for delay and energy efficient data transmission for on-chip buses and evaluate the effectiveness of our technique by focusing on the Ll cache address/data buses of a microprocessor using the SPEC2000 CINT benchmark suit. We show that our technique achieves 31% (30%) of delay improvement along with energy savings of 13% (9%) over the base case for data transmission on address (data) bus. © 2006 IEEE.

Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006

Delay and energy efficient data transmission for on-chip buses

Insertion grammars have been introduced in [1] and their computational power has been studied in several places. In [7] it is proved that insertion grammars with weight at least 7 can characterize recursively enumerable languages (modulo a weak coding and an inverse morphism), and the question was formulated whether or not this result can be improved. In this paper, we come up with a positive answer to this question, by decreasing the weight of the insertion grammar used to 5. We also give a characterization of recursively enumerable languages in terms of right quotients of insertion languages.

Fundamenta Informaticae

On characterizing recursively enumerable languages by insertion grammars

Generally, for proving universality results about rewriting P systems one considers matrix grammars in the strong binary normal form. Such grammars contain both matrices with rules used in the appearance checking mode and matrices without appearance checking rules. In the proofs of most of the universality theorems reported in the literature, appearance checking matrices are simulated by using only two membranes, while four membranes are used for simulating matrices without appearance checking rules. Thus, a way to improve these theorems is to diminish the number of membranes used for simulating matrices without appearance checking rules. In this paper we address this problem, and give first a general improved result about simulating matrix grammars without appearance checking: three membranes are shown to suffice. This result is then used to improve several universality results from various membrane computing papers, for instance, about P systems with replicated rewriting, with leftmost rewriting, with conditional communication, as well as for hybrid P systems with finite choice. © 2004 Elsevier B.V. All rights reserved.

Fulltext

Theoretical Computer Science

Rewriting P systems: Improved hierarchies

By considering string-objects and rewriting rules, we propose a variant of tissue P systems, namely, rewriting tissue P systems. We show the computational efficiency of rewriting tissue P systems by solving the Satisfiability and the Hamiltonian path problems in linear time. We study the computational capacity of rewriting tissue P systems and show that rewriting tissue P systems with at most two cells and four states are computationally universal. We also show the universality result of rewriting tissue P systems with at most one cell and five states. Finally we propose some new directions for future work. © J.UCS.

Journal of Universal Computer Science

Rewriting tissue P systems

As the CMOS technology scaled down to deep submicron level, the crosstalk effects due to the coupling capacitance between interconnection lines has become one of the main performance limiting factors. Several methods such as those based on routing strategies, skewing the timing of signals on adjacent wires, interleaving mutually exclusive buses, precharging the bus, and bus encoding technique, have been proposed to eliminate/reduce the crosstalk delay. In this work, we propose a bus encoding technique using a variant of binary Fibonacci representation to prevent crosstalk delay and give a recursive procedure to generate crosstalk delay free binary Fibonacci codewords. We show that m-bit crosstalk delay free binary Fibonacci codewords are used to encode [log 2(Fm+2)]-bit bus, where Fm+2 is the (m + 2)th Fibonacci number. So, a 32-bit bus can be encoded using 46-bit crosstalk delay free binary Fibonacci codewords.

Proceedings of the IEEE International Conference on VLSI Design

Preventing crosstalk delay using Fibonacci representation

Considerable research has been done in the area of bus-encoding techniques, for either power minimization or cross-talk elimination in system-level buses, but not both together. We propose No Adjacent Transition (NAT) coding scheme, a bus encoding technique that simultaneously reduces power consumption and eliminates cross-talk. NAT-encoding and decoding algorithms are proposed and an analytical study of power dissipation is presented.