IIT Madras is a public technical and research university located in Chennai, Tamil Nadu. Founded in 1959, it is recognised as an Institute of National Importance.

IIT Madras has been ranked as the top engineering institute in India for four years in a row by the National Institutional Ranking Framework of the MHRD

It currently offers undergraduate, postgraduate and research degrees across 16 disciplines in Engineering, Sciences, Humanities and Management. About 596 faculty belonging to science and engineering departments and centres of the Institute are engaged in teaching, research and industrial consultancy.

IIT Madras

We investigate the mechanism of drain disturb in SONOS flash memory cells. Our results show that drain disturb can be a serious concern in programmed state and is caused by injection of holes from substrate into the nitride. We identify the key factors responsible for this to be band-to-band tunneling at the drain junction and impact ionization of the channel leakage current. © 2005 IEEE.

Department of Electrical Engineering

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Department of Ocean Engineering

Department of Mechanical Engineering

IEEE International Reliability Physics Symposium Proceedings

Mechanism of drain disturb in SONOS flash EEPROMs

A novel scheme called Soft Secondary Electron Programming (SSEP) is introduced and shown to be a promising programming mechanism for scaled NOR Flash EEPROMs. SSEP involves use of an "optimum" VB that results in a lower drain disturb compared to both Channel Hot Electron (CHE) and CHannel Initiated Secondary Electron (CHISEL) mechanisms. The concept behind minimizing drain disturb is discussed. SSEP is shown to give faster programming and lower disturb than CHE at all operating conditions, and better program/disturb margin compared to CHISEL at similar program speed or disturb time. © 2005 IEEE.

Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

Soft secondary electron programming for floating gate NOR flash EEPROMs

The origin of drain disturb in NOR Flash EEPROM cells under channel initiated secondary electron (CHISEL) programming operation is identified. A comparative study of drain disturb under channel hot electron (CHE) and CHISEL operation is performed as a function of drain bias and temperature on bitcells having different floating gate length and junction depth. The disturb mechanism is shown to originate from band-to-band tunneling under CHISEL operation, unlike that under CHE operation that originates from source-drain leakage. The effect of technological parameters (channel doping and drain junction depth) on CHISEL drain disturb is studied for both the charge gain (erased cell) and charge loss (programmed cell) disturb modes. Fullband Monte Carlo device simulations are used to explain the experimental results. It is shown that methods for improving CHISEL programming performance (higher channel doping and/or lower drain junction depth or halo) increase drain disturb, which has to be carefully considered for efficient design of scaled cells.

IEEE Transactions on Electron Devices

Drain disturb during CHISEL programming of NOR flash EEPROMs - Physical mechanisms and impact of technological parameters

The impact of technological parameter (channel doping, source/drain junction depth) variation and channel length scaling on the reliability of NOR Flash EEPROM cells under channel initiated secondary electron (CHISEL) programming is studied. The best technology for CHISEL operation has been identified by using a number of performance metrics (cycling endurance of program/erase time, program/disturb margin) and scaling studies were done on this technology. It is explicitly shown that from a reliability perspective, bitcell optimization for CHISEL operation is quite different from that for channel hot electron (CHE) operation. Properly optimized bitcells show reliable CHISEL programming for floating gate length down to 0.2 μm. © 2004 IEEE.

Fulltext

Cycling endurance of NOR Flash EEPROM cells under CHISEL programming operation - Impact of technological parameters and scaling

The performance and reliability of flash EEPROM under multilevel CHannel Initiated Secondary ELectron (CHISEL) programming operation, were analyzed. Six different bitcell doping schemes were studied and optimized doping was identified based on their program and drain-disturb performance. Isolated and fully scaled (W=0.3μm) bitcells using 0.18μm technology were used, having floating gate length of 0.2-0.26μm, tunnel oxide and IPD thickness of 12nm and 20nm respectively. Cycling induced degradation was only occurred for the erased VT and not for any of the programmed VT levels.

Annual Proceedings - Reliability Physics (Symposium)

Multi-level programming of NOR flash EEPROMs by CHISEL mechanism

Drain disturb is studied in NOR flash EEPROM cells under CHE and CHISEL programming operation, before and after repeated program/erase (P/E) cycling. Drain disturb is shown to originate from band-to-band tunneling under CHISEL operation, unlike under CHE operation where it originates from source-drain leakage. Under identical initial programming time, CHISEL operation always shows slightly lower program/disturb (P/D) margin before cycling but similar P/D margin after repetitive P/E cycling when compared to CHE operation. The degradation of gate coupling coefficient that affects source/drain leakage and the increase in trap-assisted band-to-band tunneling seems to explain well the behavior of CHE and CHISEL drain disturb after cycling.

IEEE Transactions on Device and Materials Reliability

Effect of P/E Cycling on Drain Disturb in Flash EEPROMs Under CHE and CHISEL Operation

The programming performance, cycling endurance and scaling of CHISEL NOR flash EEPROMs is studied for two different (halo and no-halo) channel engineering schemes. Programming speed under identical bias, bias requirements under similar programming time, cycling endurance and drain disturb are compared. The scaling properties of programming time (at a fixed bias), bias (at a fixed programming time) and program/disturb margin are studied as cell floating gate length is scaled. The relative merits of these channel engineering schemes are discussed from the viewpoint of futuristic CHISEL cell design. © 2003 IEEE.

European Solid-State Device Research Conference

The impact of channel engineering on the performance reliability and scaling of CHISEL NOR flash EEPROMs

The impact of programming biases, device scaling and variation of technological parameters on channel initiated secondary electron (CHISEL) programming performance of scaled NOR Flash electrically erasable programmable read-only memories (EEPROMs) is studied in detail. It is shown that CHISEL operation offers faster programming for all bias conditions and remains highly efficient at lower biases compared to conventional channel hot electron (CHE) operation. The physical mechanism responsible for this behavior is explained using full band Monte Carlo simulations. CHISEL programming efficiency is shown to degrade with device scaling, and various technological parameter optimization schemes required for its improvement are explored. The resulting increase in drain disturbs is also studied and the impact of technological parameter optimization on the programming performance versus drain disturb tradeoff is analyzed. It is shown that by judicious choice of technological parameters the advantage of CHISEL programming can be maintained for deeply scaled electrically erasable programmable read-only memory (EEPROM) cells.

CHISEL programming operation of scaled NOR flash EEPROMs - Effect of voltage scaling, device scaling and technological parameters

In this paper, we report an extensive study of drain disturb in isolated cells under channel hot electron (CHE) and channel initiated secondary electron (CHISEL) has been identified to be initiated by band-to-band (BB) tunnelling as opposed to S/D leakage for CHE operation. This is verified by measurements under different temperature and on cells having different floating gate length (Lfg). The effect of program/erase (P/E) cycling on drain distrubs is explored for different control gate bias (Vcg) and Vd. After cycling the program/disturb margin has been found to decrease for the charge gain mode, while it remains constant for the charge loss mode. The program/disturb margin for CHISEL operation is slightly lower compared to CHE operation under identical (initial) programming time (Tp). However the margin becomes identical when compared after 100K P/E cycling. © 2003 IEEE.