Deleep R. Nair
Professor
+91-44-2257-4471 (Work)
Publications - 49Publications - 49
Publications - 49Publications (49)
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ArticlesPiezoelectric-on-Silicon Array Resonators with Asymmetric Phononic Crystal Tethering2017 | Institute of Electrical and Electronics Engineers Inc.
ArticlesNovel RF MEMS capacitive switches with design flexibility for multi-frequency operation2017 | Institute of Physics Publishing- ConferencesAnalysis of systematic and random variation of gate-induced drain leakage in silicon-germanium channel pFET2017 | Institute of Electrical and Electronics Engineers Inc.
- ArticlesEffects of trap-assisted tunneling on gate-induced drain leakage in silicon-germanium channel p-type FET for scaled supply voltages2016 | Japan Society of Applied Physics
- ArticlesStudy of the Effect of Surface Roughness on the Performance of RF MEMS Capacitive Switches Through 3-D Geometric Modeling2016 | Institute of Electrical and Electronics Engineers Inc.
Open Access - ConferencesDrift compensation using bulk feedback in a neural recording system based on open-gate FET2015 | Institute of Electrical and Electronics Engineers Inc.
- ArticlesEffect of germanium preamorphization implant on performance and gate-induced drain leakage in SiGe channel pFET2015 | Institute of Electrical and Electronics Engineers Inc.
- ConferencesModeling of gate-induced drain leakage mechanisms in silicon-germanium channel pFET2014 | Institute of Electrical and Electronics Engineers Inc.
- ArticlesAnalysis of gate-induced drain leakage mechanisms in silicon-germanium channel pFET2014 | Institute of Electrical and Electronics Engineers Inc.
- ConferencesA novel FinFET with dynamic threshold voltage2014 | Institute of Electrical and Electronics Engineers Inc.
- OtherA manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications, , ..., , ..., , ..., Chudzik M. (63 authors)2011 | IEEE
- Other32nm general purpose bulk CMOS technology for high performance applications at low voltage, Arnaud F., ..., , ..., , ..., Steegen A. (36 authors)2008 | IEEE
- OtherA cost effective 32nm high-K/metal gate CMOS technology for low power applications with single-metal/gate-first process, Chen X., ..., , ..., , , ..., , ..., Steegen A. (46 authors)2008 | IEEE
