A novice continuous-time delta-sigma designer is faced with an admittedly complex maze of possible design choices. The right architecture often determines how efficiently the modulator can be implemented. This paper critically examines various popular delta-sigma architectures. It concludes that a single-bit modulator with FIR feedback is a prime candidate that enables a power-efficient implementation for a variety of specifications. To support this thesis, measurement results of an audio delta-sigma modulator, designed in a 65 nm CMOS process are given. The modulator, which incorporates FIR feedback and chopping to reduce 1/f noise, achieves 98.6 dB peak SNDR in a 24 kHz bandwidth and consumes only 260 μ W from a 1.2 V supply. © 2018 IEEE.

Shanthi Pavan Y

Department of Electrical Engineering

Siddharth Baskaran

Continuous time systems

Delta sigma modulation

Feedback

FIR filters

CMOS processs

Continuous-time

DELTA SIGMA

DELTA SIGMA MODULATOR

DELTA-SIGMA ARCHITECTURE

FIR FEEDBACKS

POWER EFFICIENT

SINGLE-BIT MODULATORS

MODULATORS

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IIT Madras

What Architecture Should I Choose for my Continuous-Time Delta-Sigma Modulator?

Proceedings - IEEE International Symposium on Circuits and Systems

Chopping the operational transconductance amplifier (OTA) of the input integrator in a CT ΔΣ M is a traditional and effective way of addressing flicker noise in such modulators. Unfortunately, chopping leads to aliasing of shaped quantization noise into the signal band and degrades performance. We analyze the mechanisms of shaped-noise aliasing in OTA- RC integrators that use two-stage feedforward-compensated OTAs, and show that aliasing can be largely mitigated by using an finite impulse response feedback digital-to-analog converter with its zeros placed at multiples of twice the chopping frequency. The theory is borne out by measurement results from a single-bit CT ΔΣM, which achieves a peak SNDR of 98.5 dB in a 24-kHz bandwidth while consuming only 280 μW from a 1.8-V supply. Realized in a 180-nm CMOS technology, it achieves a 1/f noise corner of about 3 Hz when chopped at fs/24. © 1966-2012 IEEE.

IEEE Journal of Solid-State Circuits

Analysis and Design of Continuous-Time Delta-Sigma Converters Incorporating Chopping

Continuous-time Delta-Sigma Modulators (CTΔΣMs) are a compelling choice for the design of high resolution analog-to-digital converters. Many delta-sigma architectures have been published (and continue to be invented). This leaves the designer with a bewildering array of choices, many of which seem to pull in opposite directions. Further, it is often difficult to make a clear comparison of various architectures, as they have been designed for dissimilar specifications, by different design groups, and in different technology nodes. This paper examines various design alternatives for the design of power efficient single-loop continuous-time delta sigma converters. © 2016 IEEE.

2016 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2016

Design considerations for power efficient continuous-time delta-sigma converters

We present a technique for determining the coefficients of the loop filter in a continuous-time delta sigma modulator (CTDSM) from the corresponding discrete time prototype. The method, which is based on computing the moments of the feedback DAC pulse shape, enables the determination of loop filter coefficients to an arbitrary DAC pulse shape without resorting to z-domain analysis. This not only simplifies the algebra, but also gives new insights into modulator operation. The technique helps derive topologies to compensate CTDSMs with FIR feedback DACs, as well as give closed form expressions for the coefficients of the compensated modulator. Finally, we give simple formulae for coefficients to compensate for excess loop delay in CTDSMs with arbitrary DAC pulses. © 2014 IEEE.

IEEE Transactions on Circuits and Systems I: Regular Papers

Continuous-time delta-sigma modulator design using the method of moments

A 1 V 103 dB 3rd-Order Audio Continuous-Time $Delta Sigma $ ADC With Enhanced Noise Shaping in 65 nm CMOS

2015 Symposium on VLSI Circuits (VLSI Circuits)

A low-power Gm-C-based CT-&#x0394;&#x03A3; audio-band ADC in 1.1V 65nm CMOS

What Architecture Should i Choose for my Continuous-Time Delta-Sigma Modulator?

Journal	Data powered by TypesetProceedings - IEEE International Symposium on Circuits and Systems
Publisher	Data powered by TypesetInstitute of Electrical and Electronics Engineers Inc.
ISSN	02714310
Open Access	No