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Way sharing set associative cache architecture
C. J. Janraj, Tripti S. Warrier,
Published in
2012
Pages: 251 - 256
Abstract
In order to minimize the conflict miss rate, cache memories can be organized in set-associative manner. The downside of increasing the associativity is increase in the per access energy consumption. In conventional n-way set-associative caches, irrespective of the set-wise demand, each set has n cache ways at its disposal, but cache sets may exhibit nonuniform demand for these cache ways. Exploiting this property, we propose a novel cache architecture, called way sharing cache, wherein by allowing sharing of cache ways among a pair of cache sets, we obtain dynamic energy savings as high as 41% in DL1 cache with negligible performance penalty. © 2012 IEEE.
About the journal
JournalProceedings of the IEEE International Conference on VLSI Design
ISSN10639667
Open AccessNo
Concepts (13)
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    ASSOCIATIVITY
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    Cache architecture
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    CACHE SETS
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    CONFLICT MISS
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    DYNAMIC ENERGY
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    Nonuniform
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    Performance penalties
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    SET ASSOCIATIVE CACHE
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    SET-ASSOCIATIVE
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    SET-ASSOCIATIVE CACHES
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    Cache memory
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    Energy utilization
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    Embedded systems