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Conference Proceeding
VLSI architecture and design for high performance adaptive video scalingPublished in Institute of Electrical and Electronics Engineers
1999
Volume: 4
Pages: 406 - 409
In this paper, we develop an efficient architecture for video scaling based on the adaptive image scaling algorithm. We then develop the design of the computation units and perform synthesis to show that the chip area required to perform scaling from QCIF to 4CIF is about 20 mm/sup 2/ using 0.5 /spl mu/m technology.
Topics: Very-large-scale integration (55)%55% related to the paper, Image scaling (52)%52% related to the paper and Adaptive filter (50)%50% related to the paper
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About the journal
| Journal | Data powered by TypesetProceedings - IEEE International Symposium on Circuits and Systems |
|---|---|
| Publisher | Data powered by TypesetInstitute of Electrical and Electronics Engineers |
| ISSN | 02714310 |
| Open Access | No |
Authors (1)
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