Advancements in 3D-stacking technology lead to the usage of stacked DRAM as a last level cache. DRAM caches present multiple design challenges. DRAM cache tag management overhead is one of them because of large area requirement and high access time for look-up. Numerous techniques have been proposed to handle the challenges involved with the DRAM caches. We consider a design choice wherein the tag array storage is removed completely. In this work, we propose a Tagless DRAM Cache (TDC), that completely removes tag array from the DRAM cache and instead, uses the tag-Array of the SRAM last level cache (LLC) along with DRAM cache way indices to locate data in the DRAM cache. Experimental evaluation, considering 4-core configuration, shows that TDC achieves a speedup of 9.97% when compared to baseline. Further, TDC shows greater promise by providing reduction in average power consumption by 11.22% and average SRAM LLC miss penalty by 30.8%. © 2018 IEEE.