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Shakti-T : A RISC-V processor with light weight security extensions
Arjun Menon, Subadra Murugan, , Neel Gala, Kamakoti Veezhinathan
Published in Association for Computing Machinery
2017
Volume: Part F128533
   
Abstract
With increased usage of compute cores for sensitive appli-cations, including e-commerce, there is a need to provide additional hardware support for securing information from memory based attacks. This work presents a unified hard-ware framework for handling spatial and temporal mem-ory attacks. The paper integrates the proposed hardware framework with a RISC-V based micro-Architecture with an enhanced application binary interface that enables soft-ware layers to use these features to protect sensitive data. We demonstrate the effectiveness of the proposed scheme through practical case studies in addition to taking the de-sign through a VLSI CAD design ow. The proposed pro-cessor reduces the metadata storage overhead up to 4 x in comparison with the existing solutions, while incurring an area overhead of just 1914 LUTs and 2197 IP ops on an FPGA, without affecting the critical path delay of the pro-cessor.
About the journal
JournalData powered by TypesetACM International Conference Proceeding Series
PublisherData powered by TypesetAssociation for Computing Machinery
Open AccessNo
Concepts (15)
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    Computer aided design
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    Digital storage
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    Hardware
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    Hardware security
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    Integrated circuit testing
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    Memory architecture
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    APPLICATION BINARY INTERFACES
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    BUFFER OVEROW
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    CRITICAL PATH DELAYS
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    HARDWARE FRAMEWORK
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    MICRO ARCHITECTURES
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    SECURE PROCESSORS
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    SPATIAL ATTACKS
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    TEMPORAL AT-TACKS
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    Computer architecture